Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 4: The Instruction Set ArchitectureChapter ContentsThe Instruction Set ArchitectureThe System Bus Model of a Computer System, RevisitedCommon Sizes for Data TypesBig-Endian and Little-Endian FormatsMemory Map for the ARCAbstract View of a CPUThe Fetch-Execute CycleAn Example DatapathThe ARC ISAARC Assembly Language FormatARC User-Visible RegistersARC Instruction and PSR FormatsARC Data FormatsARC Pseudo-OpsARC Example ProgramA More Complex Example ProgramOne, Two, Three-Address MachinesOne, Two, Three-Address MachinesOne, Two, Three-Address MachinesAddressing ModesSubroutine Linkage – RegistersSubroutine Linkage – Data Link AreaSubroutine Linkage – StackStack Linkage ExampleStack Linkage Example (cont’)Stack Linkage Example (cont’)Input and Output for the ISATouchscreen I/O DeviceFlowchart for I/O DeviceJava Virtual Machine ArchitectureJava Pro-gram and Com-piled Class FileA Java Class FileA Java Class File (Cont’)Byte Code for Java Program4-1Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationPrinciples of Computer ArchitectureMiles Murdocca and Vincent HeuringChapter 4: The Instruction Set Architecture4-2Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationChapter Contents4.1 Hardware Components of the Instruction Set Architecture4.2 ARC, A RISC Computer4.3 Pseudo-Ops4.4 Examples of Assembly Language Programs4.5 Accessing Data in Memory—Addressing Modes4.6 Subroutine Linkage and Stacks4.7 Input and Output in Assembly Language4.8 Case Study: The Java Virtual Machine ISA4-3Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Instruction Set Architecture• The Instruction Set Architecture (ISA) view of a machine corresponds to the machine and assembly language levels.•A compiler translates a high level language, which is architecture independent, into assembly language, which is architecture dependent.•An assembler translates assembly language programs into executable binary codes.• For fully compiled languages like C and Fortran, the binary codes are executed directly by the target machine. Java stops the translation at the byte code level. The Java virtual machine, which is at the assembly language level, interprets the byte codes (hardware implementations of the JVM also exist, in which Java byte codes are executed directly.)4-4Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe System Bus Model of a Computer System, Revisited• A compiled program is copied from a hard disk to the memory. The CPU reads instructions and data from the memory, executes the instructions, and stores the results back into the memory.4-5Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationCommon Sizes for Data Types• A byte is composed of 8 bits. Two nibbles make up a byte.• Halfwords, words, doublewords, and quadwords are composed of bytes as shown below:4-6Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationBig-Endian and Little-Endian Formats• In a byte-addressable machine, the smallest datum that can be referenced in memory is the byte. Multi-byte words are stored as a sequence of bytes, in which the address of the multi-byte word is the same as the byte of the word that has the lowest address.• When multi-byte words are used, two choices for the order in which the bytes are stored in memory are: most significant byte at lowest address, referred to as big-endian, or least significant byte stored at lowest address, referred to as little-endian.4-7Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationMemory Map for the ARC•Memory locations are arranged linearly in consecutive order. Each numbered locations corresponds to an ARC word. The unique number that identifies each word is referred to as its address.4-8Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationAbstract View of a CPU• The CPU consists of a data section containing registers and an ALU, and a control section, which interprets instructions and effects register transfers. The data section is also known as the datapath.4-9Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Fetch-Execute Cycle• The steps that the control unit carries out in executing a program are:(1) Fetch the next instruction to be executed from memory.(2) Decode the opcode.(3) Read operand(s) from main memory, if any.(4) Execute the instruction and store results.(5) Go to step 1.This is known as the fetch-execute cycle.4-10Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationAn Example Datapath• The ARC datapath is made up of a collection of registers known as the register file and the arithmetic and logic unit (ALU).4-11Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe ARC ISA• The ARC ISA is a subset of the SPARC ISA.4-12Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationARC Assembly Language Format• The ARC assembly language format is the same as the SPARC assembly language format.4-13Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationARC User-Visible Registers4-14Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationARC Instruction and PSR Formats4-15Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationARC Data Formats4-16Chapter 4 - The Instruction Set ArchitectureDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationARC