Principles of Computer Architecture Miles Murdocca and Vincent Heuring Chapter 8: Input and OutputChapter ContentsSimple Bus ArchitectureSimplified Illustration of a Bus100 MHz Bus ClockThe Synchronous BusThe Asynchronous BusBus ArbitrationBridge Based Bus Arch-itectureProgrammed I/O Flowchart for a Disk TransferInterrupt Driven I/O Flowchart for a Disk TransferDMA Transfer from Disk to Memory Bypasses the CPUDMA Flowchart for a Disk TransferIntel Memory and I/O Address SpacesStandard Intel Pentium Read and Write Bus CyclesIntel Pentium Burst Read Bus CycleIntel Pentium Hold-Hold Acknow-ledge Bus CycleA Magnetic Disk with Three PlattersManchester EncodingOrganization of a Disk Platter with a 1:2 Interleave FactorMaster Control BlockMagnetic TapeMagnetic DrumSpiral Format for Compact DiskECMA-23 Keyboard LayoutThe Dvorak Keyboard LayoutBit Pad with PuckMouse and TrackballLightpenTouchscreenJoystickLaser PrinterCathode Ray TubeDisplay ControllerVHDL SpecificationVHDL Specification (cont’)Slide 378-1Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationPrinciples of Computer ArchitectureMiles Murdocca and Vincent HeuringChapter 8: Input and Output8-2Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationChapter Contents8.1 Simple Bus Architectures8.2 Bridge-Based Bus Architectures8.3 Communication Methodologies8.4 Case Study: Communication on the Intel Pentium Architecture8.5 Mass Storage8.6 Input Devices8.7 Output Devices8-3Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationSimple Bus Architecture• A simplified motherboard of a personal computer (top view):8-4Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationSimplified Illustration of a Bus8-5Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer Organization100 MHz Bus Clock8-6Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Synchronous Bus• Timing diagram for a synchronous memory read (adapted from [Tanenbaum, 1999]).8-7Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Asynchronous Bus• Timing diagram for asynchronous memory read (adapted from [Tanenbaum, 1999]).8-8Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationBus Arbitration• (a)Simple centralized bus arbitration; (b) centralized arbitration with priority levels; (c) decentralized bus arbitration. (Adapted from [Tanenbaum, 1999]).8-9Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationBridge Based Bus Arch-itecture• Bridging with dual Pentium II Xeon processors on Slot 2. (Source: http://www.intel.com.)8-10Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationProgrammed I/O Flowchart for a Disk Transfer8-11Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationInterrupt Driven I/O Flowchart for a Disk Transfer8-12Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationDMA Transfer from Disk to Memory Bypasses the CPU8-13Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationDMA Flowchart for a Disk Transfer8-14Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationIntel Memory and I/O Address Spaces8-15Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationStandard Intel Pentium Read and Write Bus Cycles8-16Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationIntel Pentium Burst Read Bus Cycle8-17Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationIntel Pentium Hold-Hold Acknow-ledge Bus Cycle8-18Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationA Magnetic Disk with Three Platters8-19Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationManchester Encoding• (a) Straight amplitude (NRZ) encoding of ASCII ‘F’; (b) Manchester encoding of ASCII ‘F’.8-20Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationOrganization of a Disk Platter with a 1:2 Interleave Factor8-21Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationMaster Control Block8-22Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationMagnetic Tape• A portion of a magnetic tape (adapted from [Hamacher, 1990]).8-23Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationMagnetic Drum8-24Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationSpiral Format for Compact Disk8-25Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationECMA-23 Keyboard Layout• Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are frequently placed in the B row.8-26Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationThe Dvorak Keyboard Layout8-27Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationBit Pad with Puck8-28Chapter 8 - Input and OutputDepartment of Information Technology, Radford University ITEC 352 Computer OrganizationMouse and Trackball• A three-button mouse (left) and a three-button trackball (right).8-29Chapter 8 - Input and OutputDepartment of Information Technology, Radford University