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EE271 Midterm Review 03 21 2022 5 55PM 7 20PM in Room E345 Last name First name Student ID Email your bag No cell phones no calculators Your phone must be turned off and kept in 2 blank scratch paper sheets 4 pages and one handwritten cheat sheet 8 5x11 both sides are allowed We will use Lockdown Browser Webcam on Canvas go to Quizzes Lockdown Browser Instructions on Canvas go to Files Exams Remember to bring your student ID or any valid ID with photo 1 Chapter 1 Technology trend ASIC flow Chapter 2 modified format Hazards Chapter 3 Chapter 4 Chapter 5 Terminology minterms prime implicants etc Logic minimization Boolean K map QM may be presented in a Finite State Machines Moore Mealy and Verilog code for FSM Specification State Diagram Transition and Output table Slides 15 22 Verilog code for Combinational circuits and Sequential circuits Operators concatenation relational etc Data types wire reg memory Concurrent Blocking Non blocking Differences between Functions and Tasks Built in Primitives SRAM model System Tasks Functions Directives Testbench timescale Also review homework assignments 2


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SJSU EE 271 - Midterm Review

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