EE 271 HW05_sol Due On : 11/11/2021 P a g e 1 | 10 Note: You must use your own Code, Outputs and Screenshots in homework assignments. Your SJSU ID must be visible in all screenshots via Remote Desktop. Q2. (5 Points): Define Setup Time and Hold Time with diagrams. 1. Setup Time Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. In other words, each flip-flop needs some time for the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This duration is known as setup time. 2. Hold Time Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. Each sequential element needs some time for data to remain stable after clock edge arrives to reliably capture data. This duration is known as hold time. Figure shows the setup and hold time for launching and capturing flip-flops. The data that was launched at the previous clock edge should be stable at the input at least setup time before the clock edge. The data that was launched at the current edge should not travel to the capturing flop before hold time has passed after the clock edge. Q3. (5 Points): Define Slack? Explain Positive and Negative Slack. Slack is defined as difference between data arrival time and data required time for a timing path. For timing path, slack determines if the design will work at the specified speed or not. A negative slack indicates that the signal arrives at the endpoint later than the time it needs to be there, and vice versa for positive slack. Negative slack for any timing path shows hold/setup time violation.EE 271 HW05_sol Due On : 11/11/2021 P a g e 2 | 10 Q4. (5 Points): If there is a chip with Setup-time violation and a chip with hold-time violation, which is worse? Why? Chip with Hold-time violation is worse because the chip with setup violation can be fixed by reducing the clock speed, however there is no feasible solution to fix a hold time violation after chip is manufactured. Q5. (5 Points): What is Multicycle Path? How can we check Hold time and Setup time violations in 5 cycle (multicycle) path? Multicycle paths are the paths in which data from launching flipflop is allowed to use multiple clock cycles to reach at capturing flipflop. In multicycle path, setup time timing constraint should be measured with respect to rising edge of the launching clock cycle to the rising edge of data capturing clock cycle. Whereas for hold time analysis should be done with respect to the rising edge of the same launching cycle. In primetime, two commands are used to identify the multicycle paths. To define 5 cycle paths for setup calculation, and to request to check hold before 4 cycles. set_multicycle_path –setup 5 –from launch/clk –to capture/D set_multicycle_path –hold 4 –from launch/clk –to capture/D Q6. (10 Points): Explain the concept of pipelining with an example. Pipelining is a concept of breaking the critical path into two or more segments and executing it concurrently to increase the throughput. Once a segment completes an operation, it passes the result to the next segment in the pipeline and fetches the next operations from the preceding segment. Figure on left shows the unpipelined laundry operation which takes total 6 hours to finish 4 loads while figure in right implements pipelining concept and finishes the 4 loads within just 3.5 hours. In pipelined operation each three task has been performed concurrently.EE 271 HW05_sol Due On : 11/11/2021 P a g e 3 | 10 Q7. (10 Points): The following figure shows flip-flop 1 to flip flop 2 with combinational logic in between. Given the following delays for both the flip flops and combinational logic elements, (Tsu=setup time, Th- Hold time, Tc2q=clk to Q and Tdelay is time delay of the logic gate) Find: a) if the device can run at 75 MHz b) if the device meets hold time requirement or not. If it does not, how can we fix it? Figure shows only one timing path: clock signal of launching flip-flop to the data pin of the capturing flip-flop. For Set-Up time constrain, Tclk > Tc2qmax + Tclmax + Tsu ; Tclk > 2ns + (5ns + 2 ns) + 3ns; Tclk should be greater than 12ns For Hold time constrain, Th < Tc2qmin + Tclmin ; Th < 1ns + (1ns + 1ns); Th should be less than 3ns a) Device can run at 75MHz as, Tclk= 1/75 MHz = 13.33ns which is more than 12ns requirement of setup time constrain.EE 271 HW05_sol Due On : 11/11/2021 P a g e 4 | 10 b) Here, data arrival time(3ns) is less than the hold time(3.5ns) which causes hold time requirement violation. We can fix this by introducing additional combinational logic delay. Q8. (5 Points): Define Static Timing Analysis. Why is it better than Dynamic Timing Analysis? Static timing analysis (STA) validates the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface. Whereas Dynamic Timing Analysis (DTA) determines the full behavior of the circuit for a given set of input stimulus vectors. Therefore, STA is better as it faster and consumes less memory compared to DTA. Q9. (5 Points): What is Skew? How can we use Skew to help fix Setup time violations? Skew is the difference in arrival of clock at two consecutive pins of a sequential elements. Clock skew is the difference in the arrival of clock signal at the clock pin of launching and capturing signal. If clock signal comes If the clock arrival time at the capturing flip-flop is greater than that at the launching flip-flop, clock skew is positive. On the contrary if the clock arrival time at capturing flip-flop is less than the launching flip-flop, clock skew is negative. We can use Positive clock skew to get more time and fix setup time violation. Q10. (10 Points): Write a design on the FPGA to display the following Hex number using four 7-segment displays: B4CD (i.e. -0.3 in decimal) Your output should be the working code and the FPGA displaying the above characters.EE 271 HW05_sol Due On : 11/11/2021 P a g e 5 | 10 Set each 7-segment display to