EE271 Advanced Digital System Design Synthesis Lecture Note 1 Introduction 1 1 VLSI Review Transistor Integration On a Single Chip 2021 Apple M1 Max Processor 53 billion transistors Moore s Law Original law number of components on IC doubles every year Later modified to doubling every 18 months later to 2 years etc Extracted from Stanford University EE271 slides 1 2 Major Challenges Power is a major problem Dennard scaling constant power density ended Extracted from Stanford University EE271 slides z H G 5 q e r F z H M 0 1 Power wall Source cpudb stanford edu 1980 Year 2013 2021 Apple M1 Max Processor 3 2GHz Clock rate and power for Intel x86 microprocessors Source Computer Organization and Design The hardware software interface D A Patterson and J L Hennessy 1 3 Major Challenges cont Increasing Design Challenges Courtesy Synopsys 188M Gates 3 6GHz 85 95W Variation 125M Gates 3 4GHz 90 105W Leakage Power 55M Gates 2 2GHz 55 95W Signal Integrity 42M Gates 1 4GHz 55 75W 7 5M Gates 300MHz 35 45W Timing Closure Timing Area 250nm 180nm 130nm 90nm 65nm 45nm 1 4 Major Challenges cont 1 5 Timing vs Power vs Area Courtesy Synopsys See the trend Die Size mm2 Gate Delay ps Capacitance fF Resistance Interconnect RC Delay ps Total Area for Repeater Cells Timing Variability Voltage V PowerDyn W VTH V IOFF nA um PowerDyn Density W cm2 PowerLeak Density W cm2 Power Density W cm2 Power Variability 90nm 65nm 45nm 1x 1x 1x 1x 1x 6 40 1x 1x 1x 1x 1x 1x 1x 50 1x 0 7x 0 7x 2x 2x 15 45 0 85x 0 7x 85x 3x 1 4x 2 5x 2x 55 1x 0 5x 0 5x 4x 5x 35 50 0 7x 0 5x 7x 9x 2x 6 5x 4x 60 1 6 Elements of Modern Design Design Representations Circuit Technologies TTL CMOS Behaviors Blocks Gates BooleanAlgebra Truth Tables Switches ASICs FPGA PAL PLA PLD Integrated Circuit Types 1 7 ASIC and General Purpose IC Application Specific Integrated Circuit ASIC Designed to perform a particular operation as opposed to General Purpose Integrated Circuits Is NOT software programmable to perform a wide variety of different tasks General Purpose Integrated Circuits Programmable microprocessors e g Intel Pentium Series Motorola HC 11 Programmable Digital Signal Processors Field Programmable Gate Arrays FPGAs Off the shelf chips that the user programs to perform simple functions but more complex than PLDs Pre fabricated logic gates programmable interconnect High power consumption high area cost per unit 1 8 VLSI Design Styles Full Custom Every transistor is designed and drawn by hand placing transistors sizing transistors routing wires Typically only way to design analog portions of ASICs Gives the highest performance but the longest design time Application Specific Integrated Circuits ASIC Gates from libraries Interconnects are unique System On Chip SoC Use blocks that were created before 1 9 Design Metrics Performance metrics in designing a digital circuit Area yield and packaging cost Speed latency delay cycle time Power consumption dissipation Throughput for pipeline applications Reliability Scalability 1 10 Optimization Trade off Area max Multi criteria optimization Multiple objectives Delay max 1 11 Overall Process of ASIC Design Verification and Implementation From ideas to design specifications Specifications List of goals that should be achieved in the design such as process clock frequencies clock jitter power supplies power dissipation die area operating temperature etc Defining functional structure and or architecture Developing and verifying HDL model Synthesizing and optimizing HDL model Physical implementation 1 12 Overall ASIC Design Flow HDL Model Behavioral RTL VHDL Verilog SystemVerilog SystemC Functional Verification Test vectors output data Synthesis Optimization Gate level netlist Functional Timing Formal Verification Test vectors output data Tech Libraries Physical Layout Optimization IC Mask FPGA Data Parasitic Extraction Functional Timing Formal Verification Test vectors output data Design Rule Checks DRC Layout Versus Schematic LVS 1 13 Standard Cell Based ASIC Physical Layout Optimization Gate level netlist Std cell Layout Libraries Floorplan Blocks chip Placement Routing Design Rules Back Annotate Mask Data Generation Layout versus Schematic Check Design Rule Check 1 14 Verifications Verification is a reverse process of the design Starts from the implementation and confirms that expectations are met Confirm the design translation from one step to the next is as expected Why Verification Code that isn t tested is probably wrong Consequences of incorrect design Catastrophic human lives financial losses late to market bad reputation Why is Verification Difficult Design complexity grows exponentially over time Our ability to verify is lagging behind Taken from EE271 Stanford University 1 15 Two Forms of Simulations Logic Simulation Design described in terms of logic gates Values are 0 1 plus others to be introduced Good for truth table verification Timing Simulation Dynamic Timing Analysis Waveform inputs and outputs Model of gate delays Are the waveform shapes expected Identification of performance bottlenecks 1 16 Types of Logic Simulators Logic Simulators HDL based Emulator based Schematic based Verilog Assertions System Verilog UVM 1 17 Where Can Things Go Wrong Everywhere Chip Design Process Specification Architecture micro arch design RTL Synthesis Place and Route P R Netlist Fabrication Chip Typical Issues In correct or ambiguous specification Bad algorithm wrong implementation logic errors connectivity mismatch typos Logic equivalence to gate netlist timing violations design rules Shorts breaks noise power Gate Netlist Logic equivalence to RTL EE271 Introduction to VLSI Systems Stanford University From Ron Ho 18 Standard Cell Libraries Standard cell libraries are tuned for different performance power and area goals For low power design the choice and mix of libraries may have a significant impact on power timing and area One key characteristic of a cell library is cell height measured in number of tracks which is the metal one M1 pitch Tall track height libraries support more complex routing with larger drive strength transistors and are tuned for performance but may have higher leakage A tall track height library has 11 or 12 tracks Low track height libraries are optimized for area efficiency with lower drive strength transistors less appropriate for high speed A 7 or 8 track library is considered as low track height library Standard track height libraries are designed to give reasonable trade off