EE271Advanced Digital System Design & SynthesisLecture Note #1 Introduction1-1VLSI Review: Transistor Integration On a Single Chip1-2❑ Moore’s Law• Original “law”: number of components on IC doubles every year• Later modified to doubling every 18 months, later to 2 years, etc.Extracted from Stanford University EE271 slides2021: Apple M1 Max Processor (53 billion transistors)1-3❑ Power is a major problem. Dennard scaling (constant powerdensity) ended.10MHzFreq.5GHz1980 Year 2013Power wallSource: cpudb.stanford.eduExtracted from Stanford University EE271 slidesMajor ChallengesClock rate and power for Intel x86 microprocessorsSource: Computer Organization and DesignThe hardware/software interfaceD.A. Patterson and J. L. Hennessy2021: Apple M1 Max Processor (3.2GHz)Increasing Design Challenges (Courtesy, Synopsys)130nm 90nm 65nm 45nmVariationLeakage PowerSignal IntegrityTiming,Area250nm 180nmTiming Closure7.5MGates 300MHz35-45W1-442MGates1.4GHz55-75W55MGates2.2GHz55-95W125MGates3.4GHz90-105W188MGates3.6GHz85-95WMajor Challenges (cont.)1-5Major Challenges (cont.)Timing vs. Power vs. Area (Courtesy, Synopsys)1-690nm 65nm 45nmDie Size (mm2)  1x 1x 1xGate Delay (ps)  1x 0.7x 0.5xCapacitance (fF) 1x 0.7x 0.5xResistance (Ω )  1x 2x 4xInterconnect RC Delay (ps) 1x 2x 5xTotal Area for Repeater Cells 6% 15% 35%Timing Variability (%) 40% 45% 50%Voltage (V)  1x 0.85x 0.7xPowerDyn (W)  1x 0.7x 0.5xVTH (V)  1x .85x .7xIOFF (nA/um)  1x 3x 9xPowerDyn Density (W/cm2)  1x 1.4x 2xPowerLeak Density (W/cm2)  1x 2.5x 6.5xPower Density (W/cm2)  1x 2x 4xPower Variability (%) 50% 55% 60%See the trend?Elements of Modern Design1-7DesignRepresentationsBehaviors Blocks GatesBooleanAlgebra Truth Tables SwitchesCircuit TechnologiesTTLCMOSASICsFPGA PAL, PLA,PLDIntegrated Circuit TypesASIC and General Purpose IC1-8❑ Application Specific Integrated Circuit (ASIC)• Designed to perform a particular operation as opposed to General Purpose Integrated Circuits• Is NOT software programmable to perform a wide variety of different tasks❑ General Purpose Integrated Circuits:• Programmable microprocessors (e.g. Intel Pentium Series, Motorola HC-11)• Programmable Digital Signal Processors.❑ Field Programmable Gate Arrays (FPGAs)• Off-the-shelf chips that the user programs to perform simple functions (but more complex than PLDs)▪ Pre-fabricated logic gates, programmable interconnect.• High power consumption, high (area) cost per-unit❑ Full Custom• Every transistor is designed and drawn by hand(placing transistors, sizing transistors, routing wires)• Typically only way to design analog portions ofASICs• Gives the highest performance but the longest designtime❑ Application Specific Integrated Circuits (ASIC)• Gates from libraries. Interconnects are unique. ❑ System On Chip (SoC)• Use blocks that were created before. 1-9VLSI Design StylesDesign Metrics1-10Performance metrics in designing a digital circuit:❑ Area (yield and packaging cost)❑ Speed (latency/delay, cycle-time)❑ Power consumption/dissipation❑ Throughput (for pipeline applications)❑ Reliability❑ Scalability❑ ...Optimization Trade-off▪ Multi-criteria optimization▪ Multiple objectives.Delay1-11maxAreamaxOverall Process of ASIC Design, Verification, and ImplementationFrom ideas to design specificationsSpecifications: List of goals that should be achieved in the design such as process, clock frequencies, clock jitter, power supplies, power dissipation, die area, operating temperature, etc…Defining functional structure and/or architectureDeveloping and verifying HDL modelSynthesizing and optimizing HDL model Physical implementation1-12Overall ASIC Design Flow1-13HDL Model (Behavioral, RTL)(VHDL, Verilog, SystemVerilog, SystemC)Functional Verification(Test vectors & output data)Synthesis & Optimization (Gate-level netlist)Functional, Timing,Formal Verification (Test vectors & output data)Tech.LibrariesPhysical Layout & Optimization(IC Mask/FPGA Data)Parasitic ExtractionFunctional, Timing, Formal Verification (Test vectors & output data)Design Rule Checks (DRC) Layout Versus Schematic (LVS)Standard-Cell Based ASIC Physical Layout &OptimizationFloorplan (Blocks/chip)Std. cellLayoutLibrariesPlacement & RoutingDesign Rule CheckGate-level netlistLayout versus Schematic CheckBack AnnotateMask Data GenerationDesign Rules1-141-15❑ Verification is a reverse process of the design:▪ Starts from the implementation and confirms that expectations are met▪ Confirm the design translation from one step to the next is as expected❑ Why Verification?▪ Code that isn’t tested is probably wrong▪ Consequences of incorrect design: Catastrophic (human lives), financial losses, late to market, bad reputation.❑ Why is Verification Difficult?▪ Design complexity grows exponentially over time. Our ability to verify is lagging behind.Verifications(Taken from EE271, Stanford University)1-16Logic Simulation• Design described in terms of logic gates• Values are 0, 1 (plus others to be introduced)• Good for truth table verificationTiming Simulation – Dynamic TimingAnalysis• Waveform inputs and outputs• Model of gate delays• Are the waveform shapes expected?• Identification of performance bottlenecksTwo Forms of SimulationsLogic SimulatorsEmulator-based Schematic-basedHDL-based1-17Types of Logic Simulators- Verilog- Assertions- System Verilog- UVM- ...Where Can Things Go Wrong? (Everywhere…)SpecificationRTLGate NetlistP&R NetlistChipArchitecture, micro-arch, designSynthesisPlace and RouteFabricationChip Design ProcessTypical IssuesIn-correct or ambiguous specificationLogic equivalence to RTLLogic equivalence to gate netlist, timing violations, design rulesShorts, breaks, noise, powerBad algorithm, wrong implementation, logic errors, connectivity mismatch, typos, …18EE271 - Introduction to VLSI Systems, Stanford University (From Ron Ho)1-19❑ Standard cell libraries are tuned for different performance, power and area goals.▪ For low-power design the choice and mix of libraries may have a significant impact on power, timing and area❑ One key characteristic of a cell library is cell heightmeasured in number of tracks, which is the metal one (M1) pitch▪ Tall track height libraries support more complex routing with larger drive strength transistors and are tuned for performance (but may have higher leakage). A tall track height