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EE 271 HW01_Solution SP 2022 P a g e 1 | 8 Q1. (10 Points): Simplify the following Boolean Algebra expression showing every possible step with the name of the property used. a. (A + B’)’ + (A + C’)(A’ + B) = A’C’ + B (A + B’)’ + (A + C’)(A’ + B) A’B + (A + C’)(A’ + B) : DeMorgan’s Theorem A’B + AA’ + AB + A’C’ + BC’ : Distributive A’B + 0 + AB + A’C’ + BC’ : Complementary A’B + AB + A’C’ + BC’ : Combination B + A’C’ + BC’ : Logical Adjacency A’C’ + B + BC’ : Associative A’C’ + B : Absorption b. AC + AB’C’+ABC = AC + AB’ AC + AB’C’+ABC AB’C’ + AC + ABC : Associative AB’C’ + AC : Absorption A(B’C’ + C) : Distributive A(C + B’) : Absorption AC + AB’ : Distributive Q2. (10 Points): Explain the difference between combinational and sequential logic with an Example. Combinational Logic are digital logic circuits in which the output is instantaneous and only a function of inputs at that time. In Verilog combinational logic synthesizes to gates. Verilog example, Assign Z = X || Y Synthesizes to an OR gate. Whereas Sequential Logic have memory to store the previous output state. Hence, the outputs are a function of the past output and the present inputs. Verilog Example: Always @ (posedge clock) Q <= D; This synthesizes into a D- flip-flop.EE 271 HW01_Solution SP 2022 P a g e 2 | 8 Q3. (10 Points): For the given truth table, a) Write the function in SOP & POS form. b) Reduce the function using KMAP. A B C Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 a) SOP : (look for 1’s) Z = A’B’C’ + AB’C’ + ABC’ + ABC POS : (look for 0’s & complement the inputs) Z = (A + B + C’)(A + B’ + C)(A + B’ + C’)(A’ + B + C’) b) K-MAP Reduction: AB C 00 01 11 10 0 1 0 1 1 1 0 0 1 0 Z = AB + B’C’EE 271 HW01_Solution SP 2022 P a g e 3 | 8 Q4. (10 Points): What is Temperature Inversion in VLSI, why does it happen and how does it affect the worst-case test conditions? At higher technology nodes (Above 90nm), the delay of CMOS circuits used to increase with increase in temperature. However, with technology nodes lower than approximately 90nm, the companies observed that on increasing temperature, delay decreases. So, the worst PVT combination (which is most harmful to performance) of a <90nm transistor is worst process, minimum voltage, and minimum temperature instead of the maximum temperature. This happens because the effect of threshold voltage dominates the effect of mobility in sub nanometer regions.EE 271 HW01_Solution SP 2022 P a g e 4 | 8 Q5. (20 Points): Use the Quine-McCluskey Method to minimize the given functions and verify it using KMAPs. a. 𝐹(𝑎, 𝑏, 𝑐, 𝑑) = 𝛴(2,3,7,9,11,13) + 𝑑(1,10,15) Implication Table: Column -1 Column -2 Column -3 1 0001 (1,3) 00-1 (1,3,9,11) -0-1 b’d 2 0010 (1,9) -001 (1,9,3,11) -0-1 b’d 3 0011 (2,3) 001- (2,3,10,11) -01- b’c 9 1001 (2,10) -010 (2,10,3,11) -01- b’c 10 1010 (3,7) 0-11 (3,7,11,15) --11 cd 7 0111 (3,11) -011 (3,11,7,15) --11 cd 11 1011 (9,11) 10-1 (9,11,13,15) 1--1 ad 13 1101 (9,13) 1-01 (9,13,11,15) 1--1 ad 15 1111 (10,11) 101- (7,15) -111 (11,15) 1-11 (13,15) 11-1 Prime Implicant Cover Table: Minterms b’d (1,3,9,11) b’c (2,3,10,11) cd (3,7,11,15) ad (9,11,13,15) 1* X 2 X 3 X X X 7 X 9 X X 10* X 11 X X X X 13 X 15* X X Hence, minimized function is, F = b’c + cd + ad K-Map: ab cd 00 01 11 10 00 01 x 1 1 11 1 1 x 1 10 1 x F = b’c + cd + adEE 271 HW01_Solution SP 2022 P a g e 5 | 8 b. 𝐹(𝑎, 𝑏, 𝑐, 𝑑) = 𝛴(0,1,2,5,6,7,8,9,10,14) Implication Table: Column -1 Column -2 Column -3 0 0000 (0,1) 000- (0,1,8,9) -00- b’c’ 1 0001 (0,2) 00-0 (0,8,1,9) -00- b’c’ 2 0010 (0,8) -000 (0,2,8,10) -0-0 b’d’ 8 1000 (1,5)* 0-01 a’c’d (0,8,2,10) -0-0 b’d’ 5 0101 (1,9) -001 (2,6,10,14) --10 cd’ 6 0110 (2,6) 0-10 (2,10,6,14) --10 cd’ 9 1001 (2,10) -010 10 1010 (8,9) 100- 7 0111 (8,10) 10-0 14 1110 (5,7)* 01-1 a’bd (6,7)* 011- a’bc (6,14) -110 (10,14) 1-10 Prime Implicant Cover Table: Minterms b’c’ (0,1,8,9) b’d’ (0,2,8,10) cd’ (2,6,10,14) a’c’d (1,5) a’bd (5,7) a’bc (6,7) 0 X X 1 X X 2 X X 5 X X 6 X X 7 X X 8 X X 9 X 10 X X 14 X Hence, minimized function is, F = b’c’ + cd’ + a’bd K-Map: ab cd 00 01 11 10 00 1 1 01 1 1 1 11 1 10 1 1 1 1 F = b’c’ + cd’ + a’bdEE 271 HW01_Solution SP 2022 P a g e 6 | 8 Q6. (10 Points): Explain static and dynamic Hazards and possible solutions to avoid them. Hazards are undesirable output changes due to temporary disturbances in inputs. Static 1-Hazard: When input changes in a combinational circuit, unwanted switching transients come into place. These occur when paths to the output have different propagation delays. This causes output to momentarily go to 0 when it should remain 1 constantly, due to input changes. This is static 1-hazard. Static 0-Hazard: This is like static 1-Hazard, but the change in inputs causes output to momentarily go from 0 to 1 to 0. Dynamic Hazard : upon input change, instead of directly changing the output state (ex. 0 to 1), output momentarily go to 1 then 0 and finally 1. Avoid: One can eliminate Hazard by inserting an additional delay in the circuit, or by adding more logic to counteract the effects. For ex. form a cover such that every pair of adjacent 1’s or 0’s is covered by the circuit. Dynamic Hazard can be avoided by eliminating both static 1 and static 0 hazards. Q7. (10 Points): Draw the circuit for the given function and fix any static 1-hazard glitches that may be present. Re-draw the circuit of Hazard free function. F(a, b, c, d) = Σ(2,3,7,8,10, 12) K-Map: ab cd 00 01 11 10 00 1 1 01 11 1 1 10 1 1 F = a’cd + b’cd’ + ac’d’EE 271 HW01_Solution SP 2022 P a g e 7 | 8 Static-1 glitch will be present when inputs switch from a’b’cd to a’b’cd’ or vice-versa. Same way static-1

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