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EE 271 HW01 Solution SP 2022 Q1 10 Points Simplify the following Boolean Algebra expression showing every possible step with the name of the property used a A B A C A B A C B A B A C A B A B A C A B DeMorgan s Theorem A B A A A B A C B C Distributive A B 0 A B A C B C Complementary A B A B A C B C Combination B A C B C Logical Adjacency A C B B C Associative A C B Absorption b AC AB C ABC AC AB AC AB C ABC AB C AC ABC AB C AC A B C C A C B AC AB Associative Absorption Distributive Absorption Distributive Q2 10 Points Explain the difference between combinational and sequential logic with an Combinational Logic are digital logic circuits in which the output is instantaneous and only a function of inputs at that time In Verilog combinational logic synthesizes to gates Whereas Sequential Logic have memory to store the previous output state Hence the outputs are a function of the past output and the present inputs Example Verilog example Assign Z X Y Synthesizes to an OR gate Verilog Example Always posedge clock Q D This synthesizes into a D flip flop P a g e 1 8 EE 271 HW01 Solution SP 2022 Q3 10 Points For the given truth table a Write the function in SOP POS form b Reduce the function using KMAP A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Z 1 0 0 0 1 0 1 1 a SOP look for 1 s Z A B C AB C ABC ABC POS look for 0 s complement the inputs Z A B C A B C A B C A B C b K MAP Reduction AB C 00 01 11 10 1 1 0 0 1 1 0 0 0 1 Z AB B C P a g e 2 8 EE 271 HW01 Solution SP 2022 Q4 10 Points What is Temperature Inversion in VLSI why does it happen and how does it affect the worst case test conditions At higher technology nodes Above 90nm the delay of CMOS circuits used to increase with increase in temperature However with technology nodes lower than approximately 90nm the companies observed that on increasing temperature delay decreases So the worst PVT combination which is most harmful to performance of a 90nm transistor is worst process minimum voltage and minimum temperature instead of the maximum temperature This happens because the effect of threshold voltage dominates the effect of mobility in sub nanometer regions P a g e 3 8 EE 271 HW01 Solution SP 2022 Q5 20 Points Use the Quine McCluskey Method to minimize the given functions and verify it using KMAPs a 2 3 7 9 11 13 1 10 15 Implication Table Column 2 1 3 1 9 2 3 2 10 3 7 3 11 9 11 9 13 10 11 7 15 11 15 13 15 00 1 001 001 010 0 11 011 10 1 1 01 101 111 1 11 11 1 1 3 9 11 1 9 3 11 2 3 10 11 2 10 3 11 3 7 11 15 3 11 7 15 9 11 13 15 9 13 11 15 Column 3 0 1 0 1 01 01 11 11 1 1 1 1 b d b d b c b c cd cd ad ad Column 1 0001 0010 0011 1001 1010 0111 1011 1101 1111 1 2 3 9 10 7 11 13 15 Minterms cd 3 7 11 15 X X X X ad 9 11 13 15 X X X X 1 2 3 7 9 10 11 13 15 b d 1 3 9 11 X X X X Prime Implicant Cover Table b c 2 3 10 11 X X X X Hence minimized function is F b c cd ad K Map ab cd 00 01 11 10 1 x 1 1 x 1 00 01 11 10 1 F b c cd ad 1 x P a g e 4 8 EE 271 HW01 Solution SP 2022 b 0 1 2 5 6 7 8 9 10 14 Implication Table Column 2 0 1 0 2 0 8 1 5 1 9 2 6 2 10 8 9 8 10 5 7 6 7 6 14 10 14 000 00 0 000 0 01 001 0 10 010 100 10 0 01 1 011 110 1 10 0 1 8 9 0 8 1 9 0 2 8 10 0 8 2 10 2 6 10 14 2 10 6 14 Column 3 00 00 0 0 0 0 10 10 a c d a bd a bc b c b c b d b d cd cd Column 1 0000 0001 0010 1000 0101 0110 1001 1010 0111 1110 0 1 2 8 5 6 9 10 7 14 Minterms Prime Implicant Cover Table b c 0 1 8 9 X X X X b d 0 2 8 10 X X X X cd 2 6 10 14 X X X X a c d 1 5 X X a bd 5 7 X X a bc 6 7 X X 0 1 2 5 6 7 8 9 10 14 Hence minimized function is F b c cd a bd K Map 00 ab cd 01 11 10 1 1 1 1 00 01 11 10 1 1 1 F b c cd a bd 1 1 1 P a g e 5 8 EE 271 HW01 Solution SP 2022 Q6 10 Points Explain static and dynamic Hazards and possible solutions to avoid them Hazards are undesirable output changes due to temporary disturbances in inputs Static 1 Hazard When input changes in a combinational circuit unwanted switching transients come into place These occur when paths to the output have different propagation delays This causes output to momentarily go to 0 when it should remain 1 constantly due to input changes This is static 1 hazard Static 0 Hazard This is like static 1 Hazard but the change in inputs causes output to momentarily go from 0 to 1 to 0 Dynamic Hazard upon input change instead of directly changing the output state ex 0 to 1 output momentarily go to 1 then 0 and finally 1 Avoid One can eliminate Hazard by inserting an additional delay in the circuit or by adding more logic to counteract the effects For ex form a cover such that every pair of adjacent 1 s or 0 s is covered by the circuit Dynamic Hazard can be avoided by eliminating both static 1 and static 0 hazards Q7 10 Points Draw the circuit for the given function and fix any static 1 hazard glitches that may be present Re draw the circuit of Hazard free function F a b c d 2 3 7 8 10 12 K Map …

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