EE 271 HW03_Solution Due On : 03/16/2022 Page 1 | 13 (10 Points): Q1. Write the following design code and testbench. Analyze the waveform exploring “gtkwave”. Analyzer and post your screenshots for the simulation output and waveform output. Test BenchEE 271 HW03_Solution Due On : 03/16/2022 Page 2 | 13 (15 Points): Q2. (a)Write the Verilog code given below. Verify your design by providing a simple testbench that covers all possible input combinations and displays the output. (b) Replace the assign statements with Gate Level Modelling. Provide the same testbench and cross verify your results with (a). The screenshot of codes (testbench and gate level modelling), output (after simulation) and waveforms will be the submission.EE 271 HW03_Solution Due On : 03/16/2022 Page 3 | 13 (10 Points): Q3. Design the following circuit using gate level modelling. Use the test bench provided. Provide Screenshots of output and waveform. (Hint: The intermediate wires here are X and X).EE 271 HW03_Solution Due On : 03/16/2022 Page 4 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 5 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 6 | 13 (20 Points): Q4. Write a design using Functions given the testbench to calculate the Factorial of a (3-bit) number. Simulation screenshot and Waveform expected.EE 271 HW03_Solution Due On : 03/16/2022 Page 7 | 13 (20 Points): Q5. Write a program Write a program to calculate Quotient and Remainder using Tasks given the testbench. Simulation and Waveform expected.EE 271 HW03_Solution Due On : 03/16/2022 Page 8 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 9 | 13 (10 Points): Q6. Write Verilog code to implement given Moore FSM and verify it using given testbench. Screenshots of your design file, simulation output and waveforms should be your submission. Note: Your waveforms must include clk (clock), rst (reset), In, Out, current state and Next State.EE 271 HW03_Solution Due On : 03/16/2022 Page 10 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 11 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 12 | 13EE 271 HW03_Solution Due On : 03/16/2022 Page 13 | 13 (5 Points): Q7. Write a program in Quartus Prime Lite to light up an LED-0 in the FPGA Board. Working code, Pin Assignment, and a picture of your lit-up FPGA with group name expected. First create a new project QP Lite. Then select your Board. Then create a Verilog file with the module name same as the project name given while creating the project. Then write the design code, compile, and select appropriate pins in Pin Planner. Then synthesize and generate programming file. Then open Program Device and select the DE10 Board and flash your program. (5 Points): Q8. What is a clock divider in Verilog? Why is it used? Explain in Brief. A clock divider divides the clock signals to increase the clock time and decrease the clock frequency. This is used to adjust the frequency of FPGA so that all the interfaced devices can synchronously communicate with each other. It is also used when we want slower clock speeds for our design. (5 Points): Q9. Write a simple Arduino code for blink led. Explain your code and the pinouts. This code uses internal LED (defined as “LED_BUILTIN”) which is hardwired to the digital pin 13 of the UNO Board. Code under “Void Loop” turns ON the LED and wait for two seconds (2000ms) to turn it OFF. After another two seconds, code again turns ON the LED and this process repeats in a