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SJSU EE 271 - Syllabus

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DEPARTMENT OF ELECTRICAL ENGINEERINGCourse Number: EE271 Section: 01 Class Code: 21926Semester: Spring 2007Exams and ProjectsHomework AssignmentsGrading Policy Important DatesMESSAGES TO EE271 STUDENTSEE271 Course Syllabus Advanced Digital System Design and Synthesis Spring 2007 SAN JOSE STATE UNIVERSITY College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING Course Number: EE271 Section: 01 Class Code: 21926 Course Title: Advanced Digital System Design and Synthesis Semester: Spring 2007 Class hours & room: Tuesday & Thursday, 19:30 – 20:45, ENGR232 Prerequisites: - EE270 - Advanced Logic Design or equivalent experience - Background in integrated circuit design is helpful - Must have self-motivations in learning CAD tools and Verilog HDL Instructor: Prof. Thuy T. Le Office Hrs: Monday & Wednesday: 14:45 – 16:30, ENGR369 Friday (project only): 11:00 – 12:00, ENGR369 Contact inf.: Email: [email protected], Web: http://www.engr.sjsu.edu/tle Phone: (408) 924-5708, Fax: (408) 924-3925 If you need to communicate with me, please try to see me in person during the office hours. If you must send me an email, please clearly specify your full-name, course, section, etc. I will not respond to email that I do not know the author or emails that have no manners. Course Description This course covers topics in the advanced design and analysis of digital circuits with HDL. The primary goal is to provide in depth understanding of logic and system design, synthesis, and optimization for area, speed and power consumption. The course enables students to apply their knowledge for the design of advanced digital hardware systems with corresponding CAD tools. Verilog HDL will be used for simulation and synthesis of the homework assignments and final design project. Topics covered include: − Review of combinational and sequential logic; − Overview of Verilog HDL with simulator and synthesizer; ⋅ Behavioral and structural models of combinational and sequential circuits ⋅ Simulation ⋅ Synthesis of combinational and sequential circuits − Timing, area, and power estimation and optimization; − Pipelining and superscalar techniques; − Advanced/high-speed digital arithmetic algorithms, design, and implementation; ⋅ Conventional and unconventional digital arithmetic ⋅ Algorithms and the design of high-speed addition/subtraction circuits ⋅ Algorithms and the design of high-speed multiplication/division circuits ⋅ Algorithm and the design of floating-point addition/subtraction circuits − Algorithms and architectures for special purpose processors; − Memory and memory control system; − Other design examples; − Embedded system design – An overview PLEASE DO NOT CONSUME FOOD IN THE CLASSROOM Page 1 of 5EE271 Course Syllabus Advanced Digital System Design and Synthesis Spring 2007 Required Reading Materials: − "EE271 Lecture Notes," by Thuy T. Le (will be distributed) − “Computer Arithmetic” by David Goldberg, Xerox Palo Alto Research Center - Appendix A of Computer Architecture – A Quantitative Approach by John L. Hennessy & David A. Patterson - Morgan Kaufmann Publishers, Inc. (available on class website) − Any “Verilog Language” books/notes. Below are few on-line documents: http://www.doulos.com/knowhow/verilog_designers_guide/ http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html− Self-research of additional reading materials based on topics covered in lecture notes Software Tools − Silos (available on class website) and/or any other Verilog simulator (such as VCS) as needed. − Synopsys Design Compiler and/or any other synthesis tools as needed. Unix Accounts on Cadence Laboratory − Rooms E289 and E291 are Cadence laboratories installed with Cadence, Synopsys, and VCS software tools. Each student can have a Unix account (one account per student, NOT per class) so if you do not have one, you can apply at www.engr.sjsu.edu/electrical/eesupp/ − For Unix tutorial materials and other documents related to Cadence laboratory, please consult Prof. Parent’s website at http://www.engr.sjsu.edu/dparent/ − If you have problems with your Unix account, please email Unix system administrator posted on the Cadence Lab website (http://www.engr.sjsu.edu/dparent/) or EE department support team at http://www.engr.sjsu.edu/electrical/eesupp/ Lectures The course will follow the selected subjects as listed on the course description. Additional theory and examples will be given and discussed in class as much as time permits. Please note that lecture materials are NOT solely based on the required text and so students are responsible for following up the lecture in order to prepare themselves for the exams. − Students are responsible for the reading the text, handouts, lecture presentations, etc. − Students are responsible for following up and keeping track of the in-class lecture materials. − Students are responsible for finding and reading additional books, papers, examples, etc. in order to gain more understanding of the materials discussed in the lectures. − Students are responsible for self-learning and using of CAD tools for assigned homework problems, projects, and for lecture discussions. Exams and Projects There will be one midterm exam, a comprehensive final exam, and a final design project. The dates of the midterm and final exams are listed as below. Since make-up exams will NOT be PLEASE DO NOT CONSUME FOOD IN THE CLASSROOM Page 2 of 5EE271 Course Syllabus Advanced Digital System Design and Synthesis Spring 2007 allowed, please make sure that you are able to attend all exams at the indicated scheduled times (from the beginning of the semester) in order to register for the course. Midterm exam: Thursday March 8, 2007 (19:30 – 20:45) Final exam: Thursday May 17, 2007 (19:45 – 22:00) Final project report due: Friday May 25, 2007 (before 5PM) − All exams are closed-book exams. o One sheet (double-side) of hand-written notes is allowed for the midterm exam and two sheets of hand-written notes are allowed for the final exam. o Summary (printed) of Verilog keywords will be provided. o Some complex information will be provided if needed. o Only basic calculators are allowed. − There will be no make-up exams (in very special circumstances, written excuse and official proofs are required for making-up exams). − Exam solutions will be discussed in class


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