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EE 271 HW04 Due On : 03/30/2022 P a g e 1 | 1 Note: You must use your own Code Outputs and Screenshots in homework assignments. Your SJSU ID must be visible in all screenshots via Remote Desktop. (20 Points): Q1. Write a Verilog design to detect the sequence “11010” using a finite state machine. On detection, assert the output logic 1. Create a testbench to verify the same. Output simulation and waveform expected. (15 Points): Q2. Design a D-flip flop and synthesize it. You can use past homework. (Note: You can use design vision gui to manually synthesize or use the synthesis script) The output should be your synthesized file dff_netlist.v with dff.v design code and tb_dff.v testbench. (10 Points): Q3. Write a simple Arduino code to interface LCD with Arduino and display “Fixed Point” in the first line and your group number in the second line as “Group (x)” where x is a number. In one paragraph, explain how the two devices communicate with each other. (Code and working LCD picture is expected) (5 Points): Q4. What is a 7-Segment Display? Explain its working in brief with pin-level diagram. (10 Points): Q5. Implement a number on the 7-segment display. Your FPGA must show your group number on any one/two of the 6 displays (7-segments). Picture, Code and Pin assignment expected. (10 Points): Q6. Implement a simple counter in the FPGA Board using Quartus Prime Lite to count until 25,000,000 or 25 Mega clock cycles. On reaching the value, toggle an LED. This counter should increment on the positive edge of the onboard 50 MHz clock. If reset, the counter resets to 0. Code and picture expected. (10 Points): Q7. Provide a block diagram of the components and peripherals you will use in the Fixed Point MAC project. (20 Points): Q8. Represents the following numbers in fixed point format Q7.9. (Your answers should be in binary and Hex). A. 13.5 B. -0.3 C. -8.6875 D.

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SJSU EE 271 - HW4

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