Lab 11: A Simple DigitalCombination LockJacob PantaloneECEN 248 – 503 TA: Ye Wang April 28th, 2016Objectives:The objective of this lab is to design a circuit that mimics the actions of a rotary combination lock on a circuit board. This means that the circuit will have to be able to detect when the proper combination is entered in order to “open the lock” and know when the wrong combination is entered in order to stay “closed”. This will be employing the usage of the Moore finite state machine.Design 1:The first experiment in lab will involve simulating the combination-lock FSM module you described in the pre-lab to ensure it works properly before attempting to load it on the FPGA board. Additionally, we will create a Verilog description of the Up/Down Counter discussed in the pre-lab. As with the combination lock FSM, we will simulate this module to ensure proper operation prior to integrating it intothe top-level module.Design 2: For the final experiment, you will integrate the modules you simulated in the previous experiment with the rotary encoder and the LCD driver modules into a top-level module. You will then synthesize and implement the top-level module and load it onto the FPGA.Conclusion:I learned the concept of taking a finite state machine and converting into Verilog while relating it to a real world application. Going from state diagram to program to implementation exposed me to the proper way to go about programming hardware in a methodical way.Post-Lab Deliverables:1. Include the source code with comments for all modules you simulated and/or implemented in lab.You do not have to include test bench code that was provided! Code without comments will not be accepted! 2. Include screenshots of all waveforms captured during simulation in addition to the test bench console output for each test bench simulation.3. Answer all questions throughout the lab manual.a. Experiment 1:i. Take a look at the simulation waveform and take note of the tests that the test bench performs. Is this an exhaustive test? Why or why not?1. Yes it is an exhaustive test even though it doesn’t go through all of the 8000 combinations. The test bench tests only certain combinations thataccount for the different possibilities and show whether other ones wouldfail.ii. Take a look at the simulation waveform and make a note in your lab write-up about how the test bench tests the operation of your Up/Down Counter.1. The up down counter test bench tests if the program counts up and down properly.4. A possible attack on your combination-lock is a brute-force attack in which every possible input combination is tried. Given the original design with a combination of three numbers between 0 and 19, how many possible input combinations exist? How about for the modified design with a combination of four numbers?If every combination were to be tried with the three number combination lock then there would be 203 possible combinations or 8000 combinations. For the modified lock design, there are 204 combinations or 160000 combinations. This would take a ton of time to get through all of these combinations in a brute-force