Lab 3: Logic Minimization withKarnaugh MapsJacob PantaloneECEN 248 – 503 TA: Ye Wang February 18, 2016Objectives:The purpose of this week’s lab assignment is to introduce a real-world application of digital electronics while demonstrating the use of Karnaugh-Maps for logic minimization. In the laboratory, I willbread-board a simple circuit which calculates the profits of a small farm. I will also feed the output of your circuit into a seven-segment display for ease of viewing.Design 1:An HP6236B DC power supply is wired to the Vcc pin and the GND pin on the (NOT) logic gate. The DC power supply will provide a constant supply of 5V to the Vcc pin. Using the other wires from the HP6236B DC power supply, wire to an input pin in the logic gate. A multimeter is then attached to the GND and an output pin of the same group within the gate as the input(s). We then measure the output voltage with the multimeter while the input voltage of the gate sweeps from 0 to 5 volts. Draw the V0 vs. Vin curve for the inverter gate. Plot the VTC.Results 1:5V DIP SwitchzDesign 2: Adding to design 1, now we must connect an odd number inverter gates. To achieve this, connect the output of one pin to the input of another and repeat until at least 5 are connected. Next, connect the last output to the first input. Finally, connect an oscilloscope to ground and the output of the final pin to record the behavior of the voltage changes.Achieve a square wave. Calculate the average delay of a single gate.Results 2:Number of inverter gates = 5Frequency = 15 HzConclusion:I understand that there is a certain voltage range for outputting a 0 or a 1 for an inverter gate. I have plotted a graph of inputs and outputs and it matches the graph given. Furthermore, the concept of connecting inverter gates in a ring and how it can operate as a clock has become clearer. I calculated the delay of a single gate and the number checks out. Post-Lab Deliverables:1. Plot the voltage transfer characteristics with Vin on x-axis and Vout on y-axis. Mark the range of voltages in output and input as Logic 0 and Logic 1. Determine the range of input voltage for which the inverter shows Logic 1 as output. Also determine the range ofinput voltage for which the inverter shows Logic 0 as output. 2. Derive the single-stage delay of the Ring Oscillator from the time period of oscillation that you see in Experiment 2. If the delay of one inverter is 10ns, what will be the frequency of the signal generated from a 21 stage ring oscillator?3. Are the signals at P, Q, R, S in Figure 2 periodic? If so, what are their time periods? How do these signals differ from the signal at node