Lab 8: Introduction toBehavioral Verilog and LogicSynthesis Jacob PantaloneECEN 248 – 503 TA: Ye Wang April 8th, 2016Objectives:The purpose of lab this week is to introduce sequential logic circuits. To start off, we will cover basic storage elements such as latches and flip-flops. You will have the opportunity to describe these components using Verilog in different ways, and then simulate them within ISE. Next, synchronous sequential circuits will be discussed. You need to combine flip-flops with combinational logic discussed inprevious labs to simulate the operation of synchronous logic. Furthermore, you will add simulation delays into your combinational logic and observe the effects it has on clock timing.Design 1:For this experiment we will begin by using structural Verilog to describe different memory components,as well as to simulate them in Xilinx ISE. To do so, simulation delays are introduced into our Verilog code. Furthermore, we will learn how to use behavioral Verilog to describe D-latch and D flip-flop so that we can build the synthesizable synchronous logic. Design 2: In this part, we will describe the 2-bit synchronous adder in Figure 6 and simulate it in Verilog. To understand the effects of combinational circuit delay on a synchronous circuit, we will begin with structural modeling method in Verilog. Then use only behavioral Verilog to describe the same circuit. Conclusion:I understand the implementation of latches and the effects of propagation delay.Post-Lab Deliverables:1. For experiment 1.e in part 1, explain the results of the simulation.2. For experiment 3 in part 1, check the waveform with internal signals. Are the latches behaving asexpected? Why or why not? 3. For experiment 1.4 in part 1, compare the waveforms you captured from the behavioral Verilog to those from the structural Verilog. Are they different? If so, how? 4. For experiment 1.e in part 2, what is the worst case propagation delay through the adder? 5. Based on the clock period you measured for your synchronous adder, what would be the theoretical maximum clock rate? What would be the effect of increasing the width of the adder on the clock rate? How might you improve the clock rate of the