Lab 5: Simple Arithmetic LogicUnitJacob PantaloneECEN 248 – 503 TA: Ye Wang March 3rd, 2016Objectives:In this lab, we will design, implement, and test a simple 4-bit Arithmetic Logic Unit (ALU) which will perform elementary computations such as addition, subtraction, and bit-wise AND. Todo so, we will learn about Two’s Complement Arithmetic and multiplexersDesign 1:In the first part, bread-board and test your addition/subtraction unit. To do so, we must utilize the4-bit carry ripple adder component SN74HC283E.Design 2: Test your 4-bit 2:1 MUX chip SN74CT257N using LEDsDesign 3:a. Connect the outputs of AND units and addition/subtraction units to the inputs of the 4-bit 2:1 MUX. b. Connect �� of the MUX to ground.c. Use LEDs to display the result coming from the MUX.d. Vary the control signals �0�1 by manually connecting them to power or ground. Verify the circuit operation matches the operation table created in the pre-lab. Conclusion:I am now comfortable using the add/subtract units and the mux chip and I understand how to use them in conjunction with the AND gate to construct a simple ALU.Post-Lab Deliverables:1. Observe and fill in the table. The result should be a 4-bit binary number. Determine whether overflow occurs or not. 2. Determine the maximum gate delay through your final ALU circuit assuming each gate has a delay of 1 unit. Highlight the critical path on the gate-level schematic. C0 C1 Operation A B Result Overflow0 0 F= A AND B 0100 0110 0100 No0 1 F= A AND B 0110 1101 0100 No1 0 F= A+B 0100 0110 1010 Yes1 0 F= A+B 0100 1101 10001 No1 0 F= A+B 1101 1001 0100 Yes1 1 F= A-B 0100 0111 1101 Yes1 1 F= A-B 0110 1001 1101 No3. Please design the overflow detecting unit in Figure 6. You can use all available signals except the signals inside the chip package. Show your process and draw a gate-level