Lab 3: Logic Minimization withKarnaugh MapsJacob PantaloneECEN 248 – 503 TA: Ye Wang February 18, 2016Objectives:The purpose of this week’s lab assignment is to introduce a real-world application of digital electronics while demonstrating the use of Karnaugh-Maps for logic minimization. In the laboratory, I will breadboard a simple circuit which calculates the profits of a small farm. I will also feed the output of your circuit into a seven-segment display for ease of viewing.Design 1:Having a constant power supply of 5V, the Vcc is then attached to four ports on the DIP switch so that we can simulate the different possibile inputs of the profit calculator. On the other side of the dipswitch, wire the inputs to ground with a 1kꭥ resister. The inputs are then attached to the profit logic, which generates the outputs P2, P1, and P0. P2 should use two AND (74ALS08) gates and an OR (74ALS32) gate as shown in the diagram, P1 needs an XOR (SN74ALS86), AND, and an OR gate in the sequence depicted below, and P0 requires a NOT (74ALS04), AND,and an OR gate as shown. These are then wired to the LED lights to determine the binary numbers.Profit LogicLED Lights5V P2DIP SwitchHCP1SP0Iz1KꭥDesign 2: Continuing from the first design, you must remove the LED lights and instead, wire the oputputs to the decoder (SN74LS47). P0 goes to port A, P1 goes to port B, and P2 goes to port C. Be sure to wire port D and the GND port to ground and the VCC port to the 5V line. You then must wire the decoder to the 7-segment display. Port f goes to port 9, port g goes to port 10 port agoes to port 7, port b goes to port 6, port e goes to port 1, port d goes to port 2, and port c goes toport 4. Finally, connect the com ports on the 7-segment display to the 5V line with a 470ꭥ resister. 5V470ꭥProfit Logic5VDecoderDecoder (SN74ALS47)Conclusion:I understand that there is a certain voltage range for outputting a 0 or a 1 for an inverter gate. I have plotted a graph of inputs and outputs, and it matches the graph given. Furthermore, the concept of connecting inverter gates in a ring and how it can operate as a clock has become clearer. I calculated the delay of a single gate and the number checks out. Post-Lab Deliverables:1. Make a table with 16 rows showing the digital inputs and outputs of your circuitobserved during lab. For input combinations not allowed by the aforementionedguidelines, provide the output values observed rather than ‘X’.2. What values does your circuit output for the “don’t cares” and why?3. Take a picture of your complete circuit with seven-segment display. Try your bestto introduce your product to John and teach him how to use