Lab 6: Introduction to LogicSimulation and Verilog Jacob PantaloneECEN 248 – 503 TA: Ye Wang March 10th, 2016Objectives:To familiarize ourselves with some of the background necessary to understand and appreciate the way modern digital design is carried out.Design 1:The objective of this lab experiment is to familiarize you with the ISE development environment. We were asked to design a 2-bit 2:1 mux and then a 4-bit 2:1 mux in Verilog and then test it.Design 2: The purpose of this experiment is to design the modules necessary to build our simple 4-bit ALU, while introducing a level of abstraction available in Verilog. Each component will be tested using ISim with the provided test benches. Design 3:For this experiment, you will use your new found Verilog skills to create the simple 4-bit ALU described inthe previous lab.Conclusion:I now understand the basics of Verilog and how I may relate it to the combinational logic that I learned prior.Post-Lab Deliverables:1. Include the source code with comments for all modules you simulated. You do not have to include testbench code. Code without comments will not be accepted! 2. Include screenshots of all waveforms captured during simulation in addition to the test bench console output for each test bench simulation.3. Examine the 1-bit, 2:1 MUX test bench code. Attempt to understand what is going on in the code. The test bench is written using behavior Verilog, which will read much like a programming language. Explain briefly what it is the test bench is doing. 4. Examine the 4-bit, 2:1 MUX test bench code. Are all of the possible input cases being tested? Why or why not? 5. In this lab, we approached circuit design in a different way compared to previous labs. Compare and contrast bread-boarding techniques with circuit simulation. Discuss the advantages and disadvantages ofboth. Which do you prefer? Similarly, provide some insight as to why HDLs might be preferred over schematics for circuit representation. Are there any disadvantages to describing a circuit using an HDL compared to a schematic? Again, which would you prefer? 6. Two different levels of abstraction were introduced in this lab, namely structural and dataflow. Provide a comparison of these approaches. When might you use one over the