Lab 4: Rudimentary AdderCircuits Jacob PantaloneECEN 248 – 503 TA: Ye Wang February 25, 2016Objectives:The purpose of this laboratory assignment is to introduce us to the design of simple combinational adder circuits. In the pre-lab assignment, we will develop the designs for a half adder, full adder, and ripple carry adder. In the lab, we will bread-board and test our adder circuits. In addition to introducing us to simple arithmetic logic, this lab assignment will reinforce the use of Karnaugh Maps. Design 1:We were asked to Implement and test our half adder design using the gates in the Integrated Circuits (ICs) provided to us. The half adder uses an XOR gate and an AND gate as shown to output the sum, ‘S’, and the carry out, ‘C’.Design 2: In this part of the lab we were asked to construct a full adder with the ICs. A full adder uses two XOR gates, and two AND gates and an OR gate as shown.Design 3:In this portion of the lab, we were required to construct a ripple-carry adder which is the combination of two full adders with the carry out connected in-between as shown.Conclusion:I am now comfortable constructing half and full adders at the logic gate level. I understand how the ripple-carry adder operates and how overflow affects the output.Post-Lab Deliverables:1. Provide all design items found in the pre-lab deliverables. If you found that a design needed corrections while executing the lab, supply the updated version of that material.2. Determine the worst case propagation delay for your full adder design. Assume each gate has the same delay of 1 unit. Show the maximum delay path in your schematic. The maximum delay path is known as the critical path for that particular combinational block.3. Design a 2-bit carry ripple adder assuming you only have half adder circuits and OR gates to work with. Draw up a schematic for your design using half adder building blocks and OR gates. Be sure the clearly label all inputs and outputs of your