ColorGrayscaleEE 200 Fall 2013Lab 13.EE 200Design ToolsLaboratory 13Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2013Lab 13.Laboratory 13 Topics• Hardware realization using an FPGA– Design Flow– Designing with the CUPL Language– Using the CUPL Compiler– Using the CUPL Simulator– Deploying the Design– Exercises: Lab 5 Parity Detector Implementation• Using XOR and D-Type Flip-Flop• Using State Machine Model2EE 200 Fall 2013Lab 13.ATMEL Documentation• Included with Lab 13 slides• ATMEL_ATF750.pdf:– data sheet• Atmel_WinCUPL_user_manual.pdf– Description of WinCUPL language and programming environment• CUPL_Reference.pdf– Detailed CUPL programming reference• MAXLOADER-2011.pdf– Programmer user guide3EE 200 Fall 2013Lab 13.Design Flow4Design Code CompileSimulateDeployTestEE 200 Fall 2013Lab 13.CUPL File Template5EE 200 Fall 2013Lab 13.Terminology• PINS correspond to physical pins on the PLD• PINNODES define buried signal nodes• Intermediate Variables arbitrary variable names that do not correspond to PINS or PINNODES and that are used to generate logic expressions6EE 200 Fall 2013Lab 13.Numbers and Bases7Number Base Decimal Value‘b’11 Binary 3‘O’201 Octal 129‘D’380 Decimal 380‘H’A3 Hexadecimal 163• All numbers are integers ranging from 0 to 232-1EE 200 Fall 2013Lab 13.Logical Operators8Description Operator Example PrecedenceNOT ! !A 1AND & A & B 2OR # A # B 3XOR $ A $ B 4EE 200 Fall 2013Lab 13.Variable Extensions• Added to variable names to indicate specific functions associated with nodes inside a PLD9Extension Side Used Description.AP L Asynchronous preset of flip-flop.AR L Asynchronous reset of flip-flop.CK L Programmable clock of flip-flop.D L D input of D-type flip-flop.OE L Programmable output enableEE 200 Fall 2013Lab 13.Design Test Bed: Parity Detector• A string of bits has even parity if the number of 1’s in the string is even• Laboratory 5 shows how to design a Moore machine that accepts a bit stream and outputs a 0 if the parity is even and a 1 if the parity is odd10EE 200 Fall 2013Lab 13.Lab 5: Parity Detector Design110S/01S/11100State DiagramPresentStateInputNextStateOutput0011010101100011DQoutputinputclockEE 200 Fall 2013Lab 13.Parity Detector Implementation I12CLK/INGNDATF750CLININININININININININVCC123456789101112 131415161718192021222324I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OEE 200 Fall 2013Lab 13.CUPL State Machine Syntax13• state_var_list: list of state bit variables• state_n: state number– decoded value (default hex) of the state_variable_list– must be unique for each PRESENT statement• statements: any conditional, next, or output statementsEE 200 Fall 2013Lab 13.Example NEXT Statements• Unconditional NEXT Statement• Conditional NEXT statement14EE 200 Fall 2013Lab 13.Unconditional Synchronous Output Statement• state_n: decoded value• var: variable name declared in the pin declarations15Pin 23 = A; /* output */ PRESENT S0NEXT S1 OUT A /* pin 23 set high */EE 200 Fall 2013Lab 13.Conditional Synchronous Output Statement• state_n: decoded value• var: variable name declared in the pin declarations16EE 200 Fall 2013Lab 13.Unconditional Asynchronous Output Statement• state_n: decoded value• var: variable name declared in the pin declarations17EE 200 Fall 2013Lab 13.Conditional Asynchronous Output Statement• state_n: decoded value• var: variable name declared in the pin declarations18EE 200 Fall 2013Lab 13.Exercise 1• Construct a state diagram representation of the FSM• How can we simplify the code using OUT statements?19EE 200 Fall 2013Lab 13.Exercise 120EE 200 Fall 2013Lab 13.Exercise 121EE 200 Fall 2013Lab 13.Parity Checker Implementation II22CLK/INGNDATF750CLININININININININININVCC123456789101112 131415161718192021222324I/OI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O0S/01S/11100State DiagramEE 200 Fall 2013Lab 13.Exercise 2• Enter and simulate the parity detector implementation I by following the instructor as they work through slides 23 through 35• Create a directory for the design (use your student drive)– C:\AtmelProjects\ParDetD123EE 200 Fall 2013Lab 13.Start the CUPL Compiler• Open the AtmelWinCupl folder under All Programs and select WinCupl• Complete WinCupl registration24EE 200 Fall 2013Lab 13.Set Working Directory25EE 200 Fall 2013Lab 13.Set Compiler Options26EE 200 Fall 2013Lab 13.Specify the PLD27EE 200 Fall 2013Lab 13.Open a New Project28EE 200 Fall 2013Lab 13.Enter and Compile Cupl Code29Device Dependent CompileEE 200 Fall 2013Lab 13.Output Files30• *.abs contains a condensed representation of the logical function to be programmed into the device• *.doc is a documentation file• *.jed is a JEDEC (Joint Electron Devices Engineering Council) file for downloading to a device programmerEE 200 Fall 2013Lab 13.Start WinSim31Launch WinSimEE 200 Fall 2013Lab 13.Open New WinSim File 32• Select New• Select your design file, for example, ParGenD1.pld, click Open• Click OKEE 200 Fall 2013Lab 13.WinSim Signal Viewer33• Default colors difficult to see on screen• View >> Colors >> Screen• Set Signals Background to white• Set Signals Grid to blackEE 200 Fall 2013Lab 13.Add Signals34• Add the input signals: CLK, INP• Add the output signals: OUTEE 200 Fall 2013Lab 13.Add Vectors35EE 200 Fall 2013Lab 13.Signal Level Options36Right Click for optionsEE 200 Fall 2013Lab 13.Set Input Signals• Green traces indicate input signals37• For low-level logic input: click on lower left edge of box• For high-level logic input: click on upper left edge of boxEE 200 Fall 2013Lab 13.Run the Simulation38Simulate• Blue traces indicate output signalsEE 200 Fall 2013Lab 13.Exercise 3• Enter and simulate parity detector implementation II• Use the same text vectors as for implementation I 39EE 200 Fall 2013Lab 13.Exercise 340EE 200 Fall 2013Lab 13.Deploying the Design41EE 200 Fall 2013Lab 13.Start Max Loader• Open the EETools folder under All Programs and select Max Loader42EE 200 Fall 2013Lab 13.Select TopMax 2 Programmer43EE 200 Fall 2013Lab 13.Select the Device to Program44EE 200 Fall 2013Lab 13.Mount the Device45EE 200 Fall 2013Lab 13.Programming Sequence• Erase the device• Load the *.jed file• Prog the device46EE 200 Fall 2013Lab 13.EE 200Design ToolsLaboratory 13Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2013Lab 13.Laboratory 13 Topics• Hardware realization using an FPGA– Design Flow–