ColorGrayscaleEE 200 Fall 2013Lab 10.EE 200Design ToolsLaboratory 10Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2013Lab 10.Laboratory 10 Topics• Testbed circuit: Lab 5 Parity Detector• Hardware realization using printed circuit boards – Multisim Electrical Rules Check (ERC)– Ultiboard quick tour– Preparing a Multisim file for transfer to Ultiboard– Transferring a design from Multisim to Ultiboard– Board outline and setup– Parts and placement– Routing methods– Design Rules Check (DRC)– Export Gerber files for manufacturing2EE 200 Fall 2013Lab 10.Parity Detector• A string of bits has even (odd) parity if the number of 1’s in the string is even (odd) • In Lab 5, you designed a Moore finite state machine that accepts a bit stream and outputs a 0 if the parity thus far is even and a 1 if the parity is oddINPUTOUTPUTCLOCK3EE 200 Fall 2013Lab 10.Parity Detector Realization using Discrete Logic (Lab 5 Exercise 2)• Today you will prepare the Multisim schematic and transfer it to Ultiboard4EE 200 Fall 2013Lab 10.Electrical Rules Check (ERC)• Verify circuit for electrical errors– GND pins connected to PWR pins• User-defined rules matrix• Tools»Electrical Rules Check• ERC Markers show error location5EE 200 Fall 2013Lab 10.ERC Rules Matrix• Select Tools»Electrical rules check• Set the desired warning or error levels by clicking on the color box • Match row by column connection6EE 200 Fall 2013Lab 10.ERC – Finding and Clearing Markers• Double-click error line in the Results tab of the Spreadsheet View• Easy to clear markers:– Tools»Clear ERC Markers7EE 200 Fall 2013Lab 10.ERC – Component Properties• Set ERC Include or Exclude status from each component’s properties window8EE 200 Fall 2013Lab 10.Exercise 1• Load the Multisim file Exercise_1_parity_detector.ms12• Perform an Electrical Error Check• What are the errors?9EE 200 Fall 2013Lab 10.Exercise 1 ERC Results10EE 200 Fall 2013Lab 10.Exercise 1 ERC Result Analysis 11• Several errors reference pin 1P1 of Switch S1• Right click Switch S1• Select Properties >> Pins• Pin 1P2 is bidirectional and connects to VDDEE 200 Fall 2013Lab 10.Exercise 1 Modify ERC• Modify the ERC to allow Connecting Bidirectional to Powerset to OK12EE 200 Fall 2013Lab 10.Exercise 1 Second ERC Run• Rerun the ERC• Locate and remove the fault13EE 200 Fall 2013Lab 10.Exercise 1• The corrected file shows no ERC errors or warnings • Save the corrected file asExercise_3_parity_detector.ms12• Exercise 3 shows how to prepare the Multisim file for transfer to Ultiboard14EE 200 Fall 2013Lab 10.The Ultiboard GUI• Similar to Multisim• Organized menus• Quick access toolbars• Design Toolbox• Spreadsheet View• Resizable Workspace• Move, hide/unhide and resize frames15EE 200 Fall 2013Lab 10.Exercise 2• Start Ultiboard and open Exercise_2_parity_detector.ewprj• Follow the instructor as they provide a tour through Ultiboard using slides 17 through 2516EE 200 Fall 2013Lab 10.Exercise 2• Show the 3D and PCB views17EE 200 Fall 2013Lab 10.Global PreferencesGeneral SettingsGeneral workspace options, mouse-wheel behavior, undo options, view options, crosshair optionsPathsSet paths for configuration files, default paths and database pathsMessage PromptsCheck prompts to display in described situationsColorsSet up color schemes for the Ultiboard workspacePCB DesignGeneral options for PCB design actions such as DRC, trace placement/deletion, router, part drag, and so onDimensionsDimension lines setup3D Options3D View settings• Options»Global Preferences18EE 200 Fall 2013Lab 10.PCB Properties• Options»PCB PropertiesAttributesDisplay attributes associated with the PCBGrids & UnitsSet design units and grid spacingCopper LayersPCB layer technology parametersPads/ViasDefault settings for pads and viasGeneral LayersAdd/remove layers from design, rename layersDesign RulesDRC parameters3D DataAdd 3D objects to the PCB (other than regular 3D parts)Favorite LayersSet layer shortcuts19EE 200 Fall 2013Lab 10.Toolbars and Menus• View»Toolbars»…– Organized based on functionality– All toolbar functions found in menus– Right-click toolbar area and toggle toolbars– Customizable (functions, location)– ToolTips20EE 200 Fall 2013Lab 10.Design Toolbox • VIEW >> Design Toolbox• Project hierarchy view• Add/edit/remove/rename designs in the current Project• Set active layer• Dim/hide/unhide layers21activelayerdimlayerEE 200 Fall 2013Lab 10.Dim/hide/unhide Layers • Click on the box to toggle the view of a given layer22Copper Bottom DimCopper Bottom Hide Copper Bottom UnhideEE 200 Fall 2013Lab 10.Spreadsheet View • View >> Spreadsheet View• Complete design summary• Find and select parts/nets• Modify most of the properties from parts, nets, pads, vias, copper areas and so on23EE 200 Fall 2013Lab 10.Selection Toolbar• Edit»Selection Filter»Enable Selecting…• Defines exactly what the mouse pointer and selection rectangles are allowed to select24EE 200 Fall 2013Lab 10.Workspace Area• Zoom in and out with the mouse-wheel• Resizable• Multiple tabs per design• Ruler bars located in top and left margins• Dim or hide layers not in use for better visibility25EE 200 Fall 2013Lab 10.Exercise 3• Preparing a Multisim file for transfer to Ultiboard• Open the Multisim file Exercise_3_parity_detector.ms12 generated in Exercise 1• Tasks to complete– Eliminate instrumentation and unnecessary components– Add headers for PCB connections– Add bypass capacitors– Select component footprints26EE 200 Fall 2013Lab 10.Exercise 3 Circuit Modifications• Delete– Oscilloscope and function generator– R2 and LED1– Switch S1– VDD and VSS power connections27EE 200 Fall 2013Lab 10.Exercise 3 Add Headers• Add headers for power, input, clock, and parity output• Use the generic HDR1X2 header28EE 200 Fall 2013Lab 10.Exercise 3 Bypass Capacitors• Shunt switching transients, maintain constant supply voltage• Place a bypass capacitor at each integrated supply pin– Value: 0.1µF, Footprint: IPC-7351/Chip-C080529EE 200 Fall 2013Lab 10.Exercise 3 Capacitor Selection• Use a Filter to help find the desired footprint• Right click C1• Properties >> Value >> Edit footprint…• In the Edit Footprint window press Select from Database• Select Filter30EE 200 Fall 2013Lab 10.Exercise 3 Resistor Footprint• Set the footprint of R1 to