ColorUntitledEE 200 Fall 2013Lab 5.EE 200Design ToolsLaboratory 5Professor Jeffrey SchianoDepartment of Electrical Engineering1EE 200 Fall 2013Lab 5.Laboratory 5 Topics• Finite state machine realization using Karnaugh maps and discrete-logic• Simulation – Multisim overview– Finite state machine• LabVIEW Programming Structures– Case Structure– While Loop2EE 200 Fall 2013Lab 5.Parity Detector• Parity bits are extra signals added to a data word to enable error checking• There are two types of Parity – even and odd• A string of bits has even (odd) parity if the number of 1’s in the string is even (odd)3EE 200 Fall 2013Lab 5.Parity Detector Project• Realize the parity detector using – Discrete logic– Programmable logic device– Embedded microcontroller– Data acquisition device (DAQ)• Compare the four implementations – The number of integrated circuits– The power consumption of the design– The ability to modify the design– The implementation cost • Repeat the process for an elevator control system4EE 200 Fall 2013Lab 5.Exercise 1• Design a Moore finite state machine that accepts a bit stream and outputs a 0 if the parity thus far is even and a 1 if the parity is odd• Realize the parity detector using only NAND gates and D-type flip-flops5INPUTOUTPUTCLOCKEE 200 Fall 2013Lab 5.Exercise 1: State Diagram6EE 200 Fall 2013Lab 5.Exercise 1: State Table7EE 200 Fall 2013Lab 5.Exercise 1: Excitation and Output Equations8EE 200 Fall 2013Lab 5.Exercise 1: Realization using NAND Gates and D-Type Flip-Flops9EE 200 Fall 2013Lab 5.NI Multisim: Course Goals• Understand the features of the Multisim user interface• Capture schematics in Multisim• Use interactive simulation to check your design• Use virtual instruments and analyses• Create custom components10EE 200 Fall 2013Lab 5.What is Multisim?• General purpose electronic design automation (EDA) tool • Schematic Capture• Analyses• Integrated Environment11EE 200 Fall 2013Lab 5.Benefits of Integrated Capture & Simulation• Preparation for simulation is as simple as drawing a circuit• Interactive Simulation• Animated Parts• Virtual Instruments• Analyses and Graphs12EE 200 Fall 2013Lab 5.Multisim in the Design Process13EE 200 Fall 2013Lab 5.The Multisim GUI• Organized menus• Quick access toolbars• Design Toolbox• Spreadsheet View• Resizable Workspace14Design ToolboxMenus Toolbars Title BarWorkspace AreaSpreadsheet ViewInstruments ToolbarEE 200 Fall 2013Lab 5.Schematic Capture• Click-and-place capture mode• Integrated with simulation• Three step process:15EE 200 Fall 2013Lab 5.Components• Symbolic representation of actual parts• All components have a symbol• Many components have a SPICE model and footprint16EE 200 Fall 2013Lab 5.Components –Virtual, Real, Layout-only17EE 200 Fall 2013Lab 5.Component Browser• Most common tool to place components• You can select:• Database• Component• Model• Footprint• Search for components18EE 200 Fall 2013Lab 5.Component Browser• To place a part, select:1.Database2.Group3.Family4.Part5.Model6.Footprint• You can also:• Search• Obtain datasheet• Print a detail report• View model19123456EE 200 Fall 2013Lab 5.Placing a Component• After selecting a component, a ghost image is attached to the mouse pointer• Click to place• Next RefDes (for example, U1) is assigned20EE 200 Fall 2013Lab 5.Placing Multi-section Components21Select any section for a new ICSelect C or D to place unused sections of U1U1, section A and B are already placed, therefore they are not selectableEE 200 Fall 2013Lab 5.Virtual Instruments• Select instruments from the Instruments toolbar22Multimeter Word Generator Agilent Function GeneratorFunction Generator Logic Analyzer Agilent MultimeterWattmeter Logic Converter Agilent Oscilloscope2-ch Oscilloscope IV-Analysis Tektronix Oscilloscope4-ch Oscilloscope Distortion Analyzer Measurement ProbeBode Plotter Spectrum Analyzer LabVIEW InstrumentFrequency Counter Network AnalyzerELVISmxInstruments*Current ProbeEE 200 Fall 2013Lab 5.Virtual Instruments – Front Panel• Double-click instrument icon to open front panel• Set instrument settings just like a real instrument23EE 200 Fall 2013Lab 5.Exercise 2• Use Multisim to simulate the parity detector in Exercise 1 • Realize the circuit using discrete-logic – CD4011BD Quad 2-Input NAND Gate– CD4013BD Dual D-Type Flip-Flop• Generate the input x using an interactive switch that toggles when x is depressed on the key board; indicate the state of the input using a blue LED• Generate a 0.5 Hz clock signal using the Agilent Fcn Gen• View the input, output, and clock using the four channel scope, assign different trace colors to the three signals• Set the simulation End time (TSTOP) to 1000 s24EE 200 Fall 2013Lab 5.Exercise 2: Schematic Capture25EE 200 Fall 2013Lab 5.Exercise 2: Function Generator26• Select the square-wave output• Set the frequency to 500 mHz• Set the output amplitude to 5 Vpp• Set the offset to 2.5 VEE 200 Fall 2013Lab 5.Exercise 2: Trace Color27• Right click wire, and select Segment Color– Use Green for the input x on scope channel B– Use Blue for the output y on scope channel CEE 200 Fall 2013Lab 5.Exercise 2: Simulation End Time• Set simulation End time (TSTOP) to 1000 s– Simulate >> Interactive Simulation Settings >>Defaults for transient analysis instruments28EE 200 Fall 2013Lab 5.Exercise 2: Simulation Results29yxclockEE 200 Fall 2013Lab 5.LabVIEW Case Structures• Case Selector Label: Contains the name of the current case and decrement and increment buttons on each side • Selector Terminal: Wire an input value, or selector, to determine which case executes30EE 200 Fall 2013Lab 5.LabVIEW Tunnels• Tunnels transfer data into and out of structures• The tunnel adopts the color of the data type wired to the tunnel31tunnelsEE 200 Fall 2013Lab 5.LabVIEW Case Structures32• Have two or more subdiagrams or cases• Execute and displays only one case at a time• An input value determines which subdiagram to executeEE 200 Fall 2013Lab 5.Exercise 2• Use the LabVIEW case structure to realize the absolute value of a real-valued input of type double33EE 200 Fall 2013Lab 5.LabVIEW While Loop34LabVIEW While LoopC Codecodedo {code }while (expression)YesFlowchartNoendconditiontrue?code• Analogous to a Do While loop in C• Code executes at least onceEE 200 Fall 2013Lab 5.While Loops•