blanksolutionsEE 200 Midterm Exam 20 March 2014Last Name (Print):First Name (Print):ID number (Last 4 digits):Section:DO NOT TURN THIS PAGE UNTIL YOU ARE TOLD TO DO SOProblem Weight Score1 252 253 254 25Total 100INSTRUCTIONS1. You have 2 hours to complete this exam.2. This is a closed book exam. You may use one 8 .5”× 11” note sheet.3. Calculators are al lowed.4. Solve each part of the problem in the space following the question. If you need more space, continue your solutionon the reverse si de lab eling the page with the question number; for example, Problem 1.2 Continue d. NOcredit will be given to solutions that do not meet this requirement.5. DO NOT REMOVE ANY PAGES FROM THIS EXAM. Loose papers will not be accepted and agrade of ZERO will be a ssigned.6. The quality of your analysis and evaluation is as important as your answers. Your reasoning must be preciseand clear; your complete English sentences should convey what you are doing. To receive credit, you mustshow your work.7. Any student caught cheating on an exam will receive a grade of zero for the exam. Additional sanctions,including assigning an XF grade, will be pursued following university guidelines.1Problem 1: (25 Points)1. (11 poi nts) Fi gure 1 shows the circuit diagram of a Moore finite state machine with input x and output y.Figure 1: Discrete logic realization of a Moore finite state machine with input x and output y.(a) (3 points) Determine expressions for DA, DB, and y in terms of x, QA, and QB.(b) (8 points) Complete the state table in Table 1.Present State Next State OutputQAQB¯x x y0 00 11 01 1Table 1: State table for the Moo re finite state machine in Figure 1.22. (10 points) Table 2 shows the state table for another fini te state m achine, with inputs x and y, and output z.The notation ¯xy indicates that the input x is in a logic low-state while the input y is in a logic high-state.For a given present state, input combinations that are not p o ssible are indicated by X. Using the fo ur-variableKarnaugh map in Figure 2, determine the excitation equati on for the input DBto the D-type flip-flop whoseoutput is QB. To receive credit, mark all the mi nterms with ei ther a 1, 0 or X (Don’t Care) in the Karnaughmap.Present State Next State OutputSymbol QAQB¯x¯y ¯xy x¯y xy zS0 0 0 S0 X S0 S0 0S1 0 1 S0 S0 S1 S2 1S2 1 1 S2 S1 X X 1Table 2: State table for a Moore finite state machine.Figure 2: Four-varia ble Karnaugh map33. (4 points) Realize the logic expressionw = xy + z¯xusing two-input NAND gates. Show all calculations needed to pl ace the expression for w in a form suitable forimplementing with NAND gates, and neatly sketch the resulting discrete-logi c circuit.4Problem 2: (25 Points)1. (12 poi nts) The circuit in Figure 3(A), with input vi(t) and output vo(t), uses a CMOS exclusive-or gate w itha low-state output voltage VL= VSS= 0 V and a high-state output voltage VH= VDD. The circuit is drivenby the pulse in Figure 3(B). I mmediately prior to the input pulse that is applied at time 0, there is no energystored in the capacitor. Neatly sketch the resulting waveforms vC(t) a nd vo(t) in Figure 4 on page 6. To receivefull credit:• Carefully l abel the maximum amplitude of the waveforms vC(t) and vo(t).• Determine the width of any pulse appearing in the output vo(t) in terms of the parameters R and C.• Show the cal culations used to derive the pulse width in terms of the parameters R and C.• Indi cate the pulse wi dth in Fig ure 4.Figure 3: (A) CMOS circuit with input vi(t) and output vo(t) and (B) the input waveform vi(t).5Figure 4: Input and output waveforms for the circuit in Figure 3.62. (13 points) The passive network in Figure 5 i mplements a filter network with input voltage f(t) and outputvoltage y(t).Figure 5: Passive filter network.(a) (7 points) The frequency response function of the network in Figure 5 has the formH(ω) =˜Y˜F= K1ω/ωc+ 1,where˜Y and˜F are the phasor representations of the output and input respectively. Express the parametersK and ωcin terms of R1, R2, and C.78(b) (6 points) Suppose that the parameters R1, R2, and C are chosen so thatH(ω) =0.5ω/100 + 1.Uisng the transfer function representation, determine the sinusoidal steady-state response y(t) of thecircuit in Figure 5 to the i nputf(t) = 4 + 8 cos(100t + 60◦).9Problem 3: (25 Points)1. (7 points) For the LabVIEW block diagram appearing in Figure 6:• (2 point) Specify if the output indicator displays a scalar, a 1D array, or a 2D array, as well as its datatype, for example, a 32-bit signed integer.• (5 points) Determine the value(s) displayed by the indicator. If the output is a 1D array, you must expressyour answer as a row or column vector with the correct dimension. If the output is a 2D array, you mustshow the correct number of rows and columns. Show work for partial credit.Figure 6: Block diagram for Problem 3 Part 1.102. (5 points) Determine the value displayed by the i ndicator in the LabVIEW block diagram appearing in Figure7. Show work fo r partial credit.Figure 7: Block diagram for Problem 3 Part 2.113. (6 points) For the LabVIEW block diagram in Figure 8, determine the value displayed by each indicator. Forstring outputs, indicate bla nk spaces between letters using the notation in Figure 9.Figure 8: Block diagram for Problem 3 Part 3.Figure 9: Notati on for indicating blank spaces.124. (7 points) For the LabVIEW block diagram appearing in Figure 10:• (2 point) Specify if the output indicator displays a scalar, a 1D array, or a 2D array, as well as its datatype, for example, a 1D array of ten 32-bit signed integers.• (5 point) Determine the value(s) displayed by the indicator. If the output is a 1D array, you must indicatethe value of every element of the array.Figure 10: Block diagram for Problem 3 Part 4.13Problem 4: (25 Points)1. (10 points) Figure 11 on page 15 shows the HDL code for realizing a Moore finite state machine using theATMEL 750CL programmable logic device. The finite state machine ha s three states S0, S1, and S2, twoinputs x and y, and one output z.(a) (7 points) Draw the state state diagram representation of the Moore finite state ma chine realized by theHDL code in Figure 11 on 15.(b) (3 points) Modify the HDL code to include an asynchronous reset that drives the finite state machine tostate S0 when the logic level on pin 4 go es from a logic-high state to a logic low-state. In the space bel ow,write the required modified and/or additional lines