EECS240 – Spring 2009Lecture 21: MatchingElad AlonDept. of EECSEECS240 Lecture 21 2Offset• To achieve zero offset, comparator devices must be perfectly matched to each other• How well-matched can the devices be made?• Not arbitrary – direct function of design choicesVi+Vi-EECS240 Lecture 21 3Device Mismatch Categories• Die-to-die• All devices on same chip (or wafer) have same characteristics• Within die (long-range)• All devices within certain region have same characteristics• Local (short-range)• Every device different, random• Usually most important source of mismatch EECS240 Lecture 21 4Sources of Local Variation• Deterministic sources:• Local poly density• Sub-90nm: stress, litho interactions, …• Random sources:• Dopant fluctuations• Line-edge roughness• Oxide traps• Focus our modeling on random variations• Deterministic handled with good layout practicesEECS240 Lecture 21 5References• M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE JSSC, vol. 24, pp. 1433 - 1439, Oct. 1989• Mismatch model• Statistical data for 2.5µm CMOS• J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and H. E. Maes, “An easy-to-use mismatch model for the MOS transistor,” IEEE JSSC, vol. 37, pp. 1056 - 1064, Aug. 2002• 0.18µm CMOS dataEECS240 Lecture 21 6Mismatch Statistics• Total mismatch set by composite of many single, independent events• Correlation distance << device dimensions• E.g., number of dopant atoms implanted into the channel• Individual effects are small: linear superposition holds• Æ Mismatch is zero mean, Gaussian distributionEECS240 Lecture 21 7Parameter Mismatch Model()2222xPPDSWLAP +=∆σ()2: standard deviation of P: active gate area: distance between device centers: measured area proportionality constant: measured distance proportionality constant, xPPPWLDASσ∆ : 0 for "good" layout≅EECS240 Lecture 21 8VTMismatch()2222TTVTVxAVSDWLσ∆= +,,2.5µm CMOS process:30 mV m35 mV mTTVNMOSVPMOSAAµµ≅≅• Mismatch in VTbetween two identical devices:• Often largest source ofoffsetEECS240 Lecture 21 9Drain Bias, VDS∆VTlargely independent of VDSEECS240 Lecture 21 10Back-Gate Bias, VSB• Mismatch can depend on VSB• Why?EECS240 Lecture 21 11Current Matching, ∆ID/IDStrong bias dependence (we knew that already)EECS240 Lecture 21 12Current FactorLWCoxµβ=EECS240 Lecture 21 13Sources of β Mismatch• Mobility variations• E.g., due to dopant variations, random defects• Oxide thickness variation• Usually very well-controlled• Edge roughnessEECS240 Lecture 21 14Edge ModelFor:Simplifies to:() () () () ()2222222222nnoxoxCCLLWWµµσσσσββσ+++=()2222222222DSWLAWLALWAWLAoxCWLβµββσ++++=() ()WLLW1 and 122∝∝σσEECS240 Lecture 21 15Orientation Effects• Si and transistors are not (perfectly) isotropic• Æ keep direction ofcurrent flow same!EECS240 Lecture 21 16Distance EffectEECS240 Lecture 21 17Process Dependence• AVttends to scale with technology • Proportional to tox• Also depends on doping levelEECS240 Lecture 21 180.18 µm CMOSEECS240 Lecture 21 19Current MatchingEECS240 Lecture 21 20Voltage MatchingEECS240 Lecture 21 21“Golden Rule” of Layout for Matching• Everything you can think of might matter• Even whether or not there is metal above the devices• How to avoid systematic errors?Ref: A. Hastings, “The art of analog layout,” Prentice Hall, 2001EECS240 Lecture 21 22Common Centroid Layout• Cancels linear gradients• Required for moderate matchingEECS240 Lecture 21 23Simulating Mismatch• Brute force: Monte Carlo• HSPICE “throws the dice”…EECS240 Lecture 21 24Simulating
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