EECS240 – Spring 2010Lecture 2: CMOS Technology and Passive DevicesElad AlonDept. of EECSEECS240 Lecture 2 2Today’s Lecture• EE240 CMOS Technology• Passive devices• Motivation• Resistors• Capacitors• (Inductors)• Next time: MOS transistor modelingEECS240 Lecture 2 3EE240 Process• 90nm 1P7M CMOS• Minimum channel length: 90nm• 1 level of polysilicon• 7 levels of metal (Cu)• 1.2V supply• Models for this process not “real”• Other processes you might see• Shorter channel length (45nm / 1V)• Bipolar, SiGe HBT• SOIEECS240 Lecture 2 4Process Options• Available for many processes• Add features to “baseline process”• E.g.• Silicide block option• “High voltage” devices (2.5V & 3.3V, >10V)• Low VTHdevices• Capacitor option (2 level poly, MIM)• …EECS240 Lecture 2 5CMOS Cross SectionMetalPolyp- substraten- wellp+ diffusionn+ diffusionEECS240 Lecture 2 6DimensionsDrawing is not to scale!EECS240 Lecture 2 7Why Talk About Passives?EECS240 Lecture 2 8Resistors• No provisions in standard CMOS• Resistors are bad for digital circuits Æ• Minimized in standard CMOS• But, often want big, well-controlledR for analog…• Sheet resistance of available layers:60 mΩ/5 Ω/5 Ω/1 kΩ/AluminumPolysiliconN+/P+ diffusionN-wellSheet resistanceLayerEECS240 Lecture 2 9How about an N-Well Resistor?EECS240 Lecture 2 10Silicide Block Option• Non-silicided layers have significantly larger sheet resistance• Even with silicide block, many non-idealities:• Temperature coefficient: R = f(T)• Voltage coefficient: R = f(V)• Manufacturing Variations5050-500-50030,000505050050020,000-80020015001600-1500100180501001000N+ polyP+ polyN+ diffusionP+ diffusionN-wellBC[ppm/V]VC[ppm/V]TC[ppm/oC]@ T = 25 oCR/ [Ω/]LayerEECS240 Lecture 2 11Resistor Temp-Co. ExampleEECS240 Lecture 2 12Voltage DependenceEECS240 Lecture 2 13Voltage CoefficientExample:Diffusion resistorÆ Applied voltage modulates depletion width(cross-section of conductive channel)Æ Well acts as a shieldp- substraten- wellp+ diffusionn+ diffusionRV1V2VB()()⎥⎦⎤⎢⎣⎡⎟⎠⎞⎜⎝⎛−++−+−+≈−=BCCoCoVVVBVVVTTRIVVR2251212121EECS240 Lecture 2 14CompensationEECS240 Lecture 2 15Resistor Matching• Types of mismatch:• Run-to-run variations• Global differences in thickness, doping, etc.• Systematic (e.g. contacts)• Random variations between devices• Run-to-run variations in absolute R value: 20+%• Can be problematic for termination, bias current, etc.• Best case: make circuit depend only on ratios• E.g., use feedback to control opamp gain• With careful layout, can get 0.1 – 1% matchingEECS240 Lecture 2 16Systematic Variations from Layout• Example:• Use unit element instead:R2R?2RREECS240 Lecture 2 17Common Centroid and DummiesExample: R1 : R2 = 1 : 2gradientR10.5 * R2 - ∆R0.5 * R2 + ∆RDummy ÆDummy ÆEECS240 Lecture 2 18Resistor Layout (cont.)Serpentine layout for large values:Better layout (mitigates offset due to thermoelectric effects):See Hastings, “The art of analog layout,” Prentice Hall, 2001.EECS240 Lecture 2 19MOSFETs as Resistors• Triode region (“square law”):• Small signal resistance:• Voltage coefficient:DSTHGSDSCVVVVRRV−−=∂∂=11DSTHGSDSDSTHGSoxDVVVVVVVLWCI >−⎟⎠⎞⎜⎝⎛−−= for 2µ()()DSTHGSTHGSoxDSTHGSoxDSDVVVVVLWCRVVVLWCVIR>>−−≈−−=∂∂=for 11µµEECS240 Lecture 2 20MOS ResistorsExample: R = 1 MΩ• Large R-values realizable in small area• Very large voltage coefficient• Applications:• MOSFET-C filters: (linearization)Ref: Tsividis et al, “Continuous-Time MOSFET-C Filters in VLSI,”JSSC, pp. 15-30, Feb. 1986.• Biasing: (>1GΩ)Ref: Geen et al, “Single-Chip Surface-Micromachined Integrated Gyroscope with 50o/hour Root Allen Variance,” ISSCC, pp. 426-7, Feb. 2002.()()102V5.0V2112001V2MΩ1VµA100111−===−==××=−=−≈THGSVVCTHGSoxTHGSoxVVVVVRCLWVVLWCRDSµµEECS240 Lecture 2 21Resistor Summary• No or limited support in standard CMOS• Large area (compared to FETs)• Nonidealities:• Large run-to-run variations• Temperature coefficient• Voltage coefficients (nonlinear)• Avoid them when you can• Especially in critical areas, e.g.• Amplifier feedback networks• Electronic filters• A/D converters• We will get back to this point EECS240 Lecture 2 22Capacitors• Simplest capacitor:substrate• What’s the problem with this?EECS240 Lecture 2 23Capacitors• “Improved” capacitor:substrate• Is this only 1 capacitor?EECS240 Lecture 2 24Capacitor OptionsBigBig~ 1000Junction caps120Poly-substrate50Metal-poly30Metal-substrate302050Metal-metal25101000Poly-poly (option)BigHuge10,000GateTC[ppm/oC]VC [ppm/V]C [aF/µm2]TypeEECS240 Lecture 2 25MOS Capacitor• High non-linearity, temperature coefficient• But, still useful in many applications, e.g.:• (Miller) compensation capacitor• Bypass capacitor (supply, bias)EECS240 Lecture 2 26Capacitor Layout• Unit elements• Shields:• Etching• Fringing fields• “Common-centroid”• Wiring and interconnect parasiticsRef.: Y. Tsividis, “Mixed Analog-Digital VLSI Design and Technology,” McGraw-Hill, 1996.EECS240 Lecture 2 27MIM Capacitors• Some processes have MIM cap as add-on option• Separation between metals is much thinner• Higher density• Used to be fairly popular• But not as popular now that have many metal layers anywaysEECS240 Lecture 2 28Capacitor Geometries• Horizontal parallel plate• Vertical parallel plate• CombinationsRef: R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors,” JSSC March 2002, pp. 384-393.EECS240 Lecture 2 29“MOM” Capacitors• Metal-Oxide-Metal capacitor. Free with modern CMOS.• Use lateral flux (~Lmin) and multiple metal layers to realize high capacitance valuesEECS240 Lecture 2 30MOM Capacitor Cross Section• Use a wall of metal and vias to realize high density• More layers – higher density• May want to chop off lower layers to reduce Cbot• Reasonably good matching and accuracyEECS240 Lecture 2 31Distributed Effects• Can model IC resistors as distributed RC circuits.• Could use transmission line analysis to find equivalent 2-port parameters.• Inductance negligible for small IC structures up to ~10GHz.EECS240 Lecture 2 32Effective Resistance• High frequency resistance depends on W, e.g.:• W=1µ 10kΩ resistor works fine at 1GHz•