1UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Homework #1 EECS 240 Due Thursday, February 5, 2009 Use the EECS240 90nm CMOS process in all homeworks and projects unless otherwise noted. The SPICE model and instructions for running the simulator are available on the course website. 1. As a brief review of some of the basic analysis you learned in EE140, in this problem we will analyze the simple amplifier circuit shown below. You can assume that the small signal output resistance (ro) of the transistor is infinite, and that the only parasitic capacitance associated with the transistor is its Cgs. a. Draw the small signal model of this amplifier. b. As a function of the transistor’s gm and the resistor values Rs and Rf, what is the small signal gain (Vo/Vi) of the amplifier? c. What is the 3dB bandwidth of this amplifier? 2. In this problem we will look at the design of MOM capacitors in our 7-level metal process. Unless otherwise noted, you should assume that all metal layers have a thickness T = 0.2µm, minimum width W = 0.14µm, minimum horizontal spacing S = 0.14µm, vertical spacing H = 0.2µm, and that the insulator is SiO2. You can assume that the separation of the lowest layer of metal from the substrate is also H = 0.2µm, and that the inter-layer vias have the same width as the wires they are connected to. For simplicity, you can ignore fringing fields in all of these calculations. a. What is the maximum capacitance density (in fF/µm2) you can achieve with a simple horizontal parallel plate? What is the ratio of capacitance to bottom plate parasitic? b. What is the maximum capacitance density (still in fF/µm2) you can achieve with a vertical parallel plate? Now what is the ratio of capacitance to bottom plate parasitic? c. In some processes, placing an inter-layer via requires the metal line to be wider than the minimum allowed. For this problem, let’s assume that a metal line with a via must be at least 0.21µm wide. In this case (and still ignoring fringing fields), what structure gives you the highest capacitance density, and what is that density? 3. In this problem you will need to run HSPICE (or whatever your favorite simulator is). For some of the problems you should access internal device parameters such as gm or VTH – in HSPICE, you can access these with a statement like: .print m1_vth=par(‘lv9(m1)’)2(You can find the names of the various transistor parameters you might want to look at in the HSPICE manual, which can be accessed from the instructional machines – see the link on the course website.) For this problem, you should plot the results for all of the process corners provided in the library (i.e. SS, TT, FF). Unless otherwise specified, use minimum length transistors with W=1µm and a maximum |VGS| and |VDS| of 1.2V. a. Plot the magnitude of the threshold voltage of an NFET and PFET as a function of channel length L. You should sweep L from 90nm to 500nm – be sure to use a step size small enough to measure a smooth curve. b. Plot the gm versus VGS of an NFET on a linear and log scale, biasing the transistor with VGS = VDS. c. Plot gm/ID as a function of |VGS| (still with VGS = VDS) for an NFET and PFET with L=90nm, 180nm, and 360nm. Then, use this data to plot V* = 2ID/gm as a function of |VGS|. d. Plot the output resistance ro and DC gain gmro versus VDS for an NFET and PFET. You should bias the transistors with V* = 200mV. What is the allowed output swing to maintain a DC gain of 80% of the peak value? e. Plot fT and fT·(gm/ID) as a function of |VGS-VT| for L=90nm, 180nm, and 360nm. You should set VDS = VGS and vary |VGS-VT| from 0 to 500mV. What is the V* that achieves the maximum fT·(gm/ID) for each channel length?. Keep these results handy for future design
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