1UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Homework #3 EECS 240 Due Thursday, March 6, 2008 Use the EECS240 0.18µm CMOS process in all home works and projects unless noted otherwise. In this homework you may use just the typical (tt) device parameters. 1. Pole-Zero Doublets: In this problem we will looking at the behavior of the circuit shown below in order to gain some intuition into the origin and response of pole-zero doublets. a. Derive the transfer function H(s) = Vout(s)/Vin(s) of the circuit. What are the DC gain (Av0), the location of the zero (ωz), and the location of the pole (ωp) as a function of R1, R2, C1, and C2? b. Now let’s look at the step response of this circuit. Immediately after the step is applied, what is the value of Vout? c. Derive an expression for Vout(t) when Vin(t) is a 1V step, and sketch these responses for two representative cases: (1) ωz > ωp, and (2) ωp > ωz. Hint: you do not need to perform any inverse Laplace transforms to get the analytical expression. d. For parts d. and e. of this problem, we will consider the following transfer function (with ωp1, ωp2, and ωz all real and positive) : ()()()121()11zppsHsssωωω+=++ Sketch ||H(jω)|| as a function of ω for (1) ωp1 < ωz < ωp2 and (2) ωp1 < ωp2 < ωz. e. Sketch the time domain step response of H(s) for cases (1) and (2). Will the step response ever overshoot its final value in these two cases? Hint: you may want to find an H1(s) and H2(s) such that H(s) = c1H1(s) + c2H2(s). – i.e., you should use a partial fraction expansion. 2. Switched-capacitor amplifier: What is the total noise variance at the output of the switched capacitor amplifier shown below at the end of a complete cycle (i.e., during φ2)? You can assume that the OTA is simply implemented by an NMOS common-source stage with a given gm and infinite ro. Vi VoCfCs+-1φ1φ1φ1φ2φ2φ23. Gain Boosted Cascode: This problem will focus on the gain-boosted cascode amplifier shown below. To simplify the analysis, you can ignore the ro of the transistors and all of the capacitors except for those explicitly drawn in the diagram. a. What is the frequency response H(s) = v3(s)/v1(s) of this amplifier? Approximately what is the unity gain frequency of the amplifier? b. Approximately what conditions are required to guarantee that the gain boosting feedback loop maintains at least 45º of phase margin? You should provide your answer in terms of gm1, gm2, gm3, R3, C1, C2, and C3. c. Assuming the current sources are ideal, what is the total noise variance at the output of the amplifier? An approximate answer will receive full credit, but for bonus points you can solve for the impact of all of the noise sources. You may find partial fraction expansions handy to avoid the need to do any additional frequency response integrations beyond the first and second order ones provided in the lecture
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