1UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences E. Alon Homework #3 EECS 240 Due Thursday, March 5, 2009 Use the EECS240 90nm CMOS process in all home works and projects unless noted otherwise. In this homework you may use just the typical (tt) device parameters. 1. Pole-Zero Doublets: In this problem we will be looking at the behavior of the circuits shown below in order to gain some intuition into the origin and response of pole-zero doublets. R1C2R2ZinR1C2R2ZinC1R1R2ZinR1R2ZinC1(i) (ii)(iii)(iv) a. Let’s start by looking at circuits (i) and (ii). Without doing any math, will the impedance of circuit (ii) always be lower, higher, or the same as circuit (i)? b. Derive the impedance Zin(s) of circuits (i) and (ii). c. Now derive and sketch the time-domain voltage response of circuits (i) and (ii) to a current step. Hint: immediately after the current step, what is the voltage across circuit (ii)? What is the final value of the voltage? d. Derive the impedance Zin(s) of circuits (iii) and (iv). e. Now sketch the time-domain voltage response of circuits (iii) and (iv) to a current step. While you can certainly derive the response of circuit (iv) using inverse Laplace transforms and partial fractions, you may find it significantly easier to use your answers from the previous sections to come up with an approximate expression instead (you will receive full credit for coming up with an appropriate approximation). 2. Switched-capacitor amplifier: What is the total noise variance at the output of the switched capacitor amplifier shown below at the end of a complete cycle (i.e., during φ2)? You can assume that the OTA is simply implemented by an NMOS common-source stage with a given gm and infinite ro. Vi VoCfCs+-1φ1φ1φ1φ2φ2φ23. Gain Boosted Cascode: This problem will focus on the gain-boosted cascode amplifier shown below. To simplify the analysis, you can ignore the ro of the transistors and all of the capacitors except for those explicitly drawn in the diagram. a. What is the frequency response H(s) = v3(s)/v1(s) of this amplifier? Approximately what is the unity gain frequency of the amplifier? b. Approximately what conditions are required to guarantee that the gain boosting feedback loop maintains at least 45º of phase margin? You should provide your answer in terms of gm1, gm2, gm3, C1, C2, and C3. c. Assuming this amplifier is used in unity gain feedback, what conditions are required to guarantee that the gain boosting feedback loop does not introduce any significant pole-zero doublets that might limit the settling response? d. In order to meet the criteria from parts b) and c) and assuming that C1 = C3 = 100fF, C2 = 1pF, V*M1 = 200mV, and V*M2 = 100mV, what are the minimum and maximum
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