Design Rules: Bridges between technology capability and design considerationsLayout Design RulesMOS transistorp-p-epip well n wellp+n+gate oxideAl (Cu)tungstenSiO2SiO2TiSi2Dual-Well Trench-Isolated CMOSfield oxideDesign RulesInterface between the circuit designer and process engineerGuidelines for constructing process masksUnit dimension: minimum line widthscalable design rules: lambda parameterabsolute dimensions: micron rulesRules constructed to ensure that design works even when small faberrors (within some tolerance) occurA complete set includesset of layersintra-layer: relations between objects in the same layerinter-layer: relations between objects on different layersλλλλ is half of the minimum feature size in a given process (e.g., min. gate length).Descriptions of a digital ICPhysicalcross sectionLogic GateCircuit SchematicWafer/dieentity inverter isport (I1 :in Bit; O1 out Bit);end inverterHDLPhysical LayoutCMOS Process LayersLayer ColorWell (p,n) YellowActive(p+,n+) GreenSelect(n+,p+) GreenPoly RedMetal1 BlueMetal2 MagentaContact to active BlackContact to poly blackvia blackStickColor BWLayout Design rules Design rulesIntra-Layer Design Rules Contacts and Vias1Contacts:Metal 1 to activeMetal 1 to poly 1Metal 1 to poly 2Vias:Metal 2 to metal 1Metal ? to metal ?Stack Vias (not always allowed):Via directly on top of contactsWell and SelectSelectActive with select around it is doped the same type as the wellActive without select is doped the same type as the substrateCircuit SchematicCMOS Inverter LayoutCMOS Inverter Layoutn-wellA A’np-substrateFieldOxidep+n+InOutGNDVDD(a) Layout(b) Cross-Section along A-A’AA’Options•merged contacts•stack viasGNDIn VDDOutn-select conventionp-substraten+(well plug)p+(substrate plug)CMOS Transistor : Stacked Wide TransistorsStacked Wide Transistors (W >> L)W >> LStrong current driveNo bendsSource/drain share regions: reduced capacitanceCMOS Transistor : Ring Transistors (Wide)Ring Transistors (W > L)Maximum W/L for a given CD(drain inside).No channel edge ⇒ no edge effects.Circular shape best (uniform channel length, no corners), but not always allowed.CMOS Transistor : Very Wide Waffle TransistorsWaffle Transistors (W >> L)Large W/L for a given area.Low parasitic source/drain capaictances.Diagonal wires are useful, but not always allowed.Low source, drain, and gate series resistances.CMOS Transistor : Long Serpentine TransistorsLong Transistors (W << L)W << L (very weak current drive; very large ON resistance)One large gate covers the entire serpentine channelUseful for load pull-up