EE534VLSI Design SystemLecture 12:Chapter 8 &9Sequential logic circuits design Sequential Logic circuitsThe logic circuits considered thus far are called combinational logic circuits. Their output depend only on the present value of input. This implies that these circuit do not have memory.Another class of the logic circuit that incorporate memory are called sequential logic circuits; that is, their output depend not only the present value of the input, but also on the previous history of inputs. Shift registersand flip-flopsare typical examples of such circuits.Sequential LogicCombinational circuits’ output is a function of the circuit inputs and a delay timeSequential circuits’ output is a function of the circuit inputs, previous circuit state, and a delay timeTerminology for Sequential CircuitsSequential logic circuits: circuit output depends both on the inputs and the present state (which is set by the preceding inputs)Multivibrator circuits: (regenerative circuits, circuits with positive feedback) output of the circuits is intentionally connected back as inputbistable element: flip flop (FF), register, latch (input can see through output during the enabling clock)astable element: oscillator, clock generatormonostable element: pulse generatorSequential LogicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsLatches vs FlipflopsLatcheslevel sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent modeinput sampled on the falling edge of the clock is held stable when clock is low (or high) - hold modeFlipflops (edge-triggered)edge sensitive circuits that sample the inputs on a clock transition- positive edge-triggered: 0 → 1- negative edge-triggered: 1 → 0built using latches (e.g., master-slave flipflops) Flip-flop: not transparent—reading input and changing output are separate events.Memory element parametersSetup time: time before clock during which data input must be stable.Hold time: time after clock event for which data input must remain stable.clockdataDynamic latchStores charge on inverter gate capacitance:Latch operationφ = 0: transmission gate is off, inverter output is determined bystorage node.φ = 1: transmission gate is on, inverter output follows D input.Setup and hold times determined by transmission gate—must ensure that value stored on transmission gate is solid.Latch LayoutD Q’VDDVSSφ’φCMOS RS Fip FlopThe operation sequence of CMOS R-S Latch is following.For example: If S = logic 1 and R = logic 0, then MN1, is turned on, Mp1, is cut off, and goes low.With = R = logic 0, then both MN3and MN4 are cut off, both MP3and Mp4are biased in a conducting state so that the output Q goes high. With Q = logic 1, MN2 is biased on, Mp2is biased off, and the flip-flop is in a set condition. When S goes low, MN1, turns off, but MN2remains conducting, so the state of the flip-flop does not change. QQFlip FlopFlip- flops are bistable circuits usually formed by cross-coupling two NOR gates. The output of the two NOR circuits are connected back to the inputs of the opposite NOR gates.CMOS R-S Fip Flop (cont.)When S = logic 0 and R = logic 1, then output Q is forced low, output goes high, and the flip-flop is in a reset condition. Again, a logic 1 at both S and R is considered to be a forbidden or a non-allowed condition, since the resulting outputs are not complementary. QSR Flip Flopdisallowed0011reset1010set0101memoryQQ00QQRSSRQQSR-Flip Flop (SR FF)SRQSRQSRQ Q01010011Q100Q010SRQQQSRQSRQQ10101100Q101Q011QQquiescent statecharacteristic tablesetresetforbiddenLater state underterminable if S/R switch simultaneously!!NOR basedNAND basedOther LatchesClocked SR latchAdds clock input. Latch output can only be set/reset when clk=1 (or clk=0)Other latch types:JK latch: Removes “not allowed” state - toggles when inputs are both 1T latch: Toggles when input = 1D latch: Output = inputClocked NOR based SR latched Clocked D LatchclockD LatchQDDQ!Qclockclocktransparent modehold mode22 transistors!TG MUX Based Latch Implementation: Version 1QDclkclk!clk!clkclkinput sampled(transparent mode)feedback(hold mode)clkD LatchQD10 transistors!TG-Mux-D Latch: Version 2Re-arrange inverters to reduce transistor count: 8 transistorsFunction of circuit shown on the rightTG Mux D Latch: Version 3Rearrange transistors more: Use “clock” to tristate the inverters internallyWe will use this circuit again later…CK=1: Inverter is activeCK=0: Inverter is tri-statedClocked JK- Latch/flip flopsaddition of clock (synchronous)elimination of forbidden inputs: JK flip-flop has defined behavior for all four input combinationsmay race when J=K=1 during φ=1latch: any input is reflected at the output after a nominal delay (latch is open when φ=1)All of the SR latched circuits discussed above are asynchronousSwitches its state due to feedback(toggle)Problem: during toggling mode the output of the circuit oscillates continuouslyuntil either the clock becomes inactive or one of the input signal goes to zero.SRQQQJKφQJKQJnKnQn+100110101Qn01Qn(b)(c)Q(a)φCKCKCK1111Master-Slave Flip-FlopBy cascading two level-sensitive latches, one type of edge triggered flip-flop is createdJK can be used for first stage so that no input combinations are invalidSR is then used for the second stage because inputs cannot be invalidMaster-Slave Flip-FlopSRQQQQSRQQJKφMASTERSLAVEQJKQφPRESETCLEARSIRIMaster-slave solves racing problems by two-stageHowever, when φis high, any glitch or spike in J will be caught in the Master stage: 1’s catching or level sensitive. It can only be avoided by making φto be high for a very short time or edge triggered.Circuit is never transparent i.e two step processMaster-slave operationφ = 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so output does not change.φ = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value.Master-slave operationSRQQQQSRQQProblem: A narrow spike or glitch in one of the input may set or reset the master, whichwill then be propagated into the slave stage during the following phase.Shortcomings of previous approaches…RS flip-flop: Has an illegal input combination that causes togglingJK flip-flop: Can still toggle if