EE534VLSI Design SystemLecture 14:Design for TestabilityIC PackagingPart 1: Design for TestabilityWhat is it?Why do we need it?How do we get it?TestabilityWhy is testing so important in IC’s?Typical device may contain 120,000,000 transistors1 bad transistor means that the part probably will not work correctlyQuestion: How do you make sure every single transistor is working?TerminologyThe terms used in testability and reliability analysis can be very confusing…A fault is some sort of flaw or mistake in the systemA failure is some sort of observably incorrect behavior in the systemNot every fault is a failure!For example, if a system has a redundant component, a fault in one component will not lead to a failureAside: Measuring QualitySo why the concern about faults and failures?You want to make sure that you are shipping products that work!In volume manufacturing, there are two ratios of concern:Yield: Of all the parts I make, how many do I consider “good”?Product quality: Of all the parts that I ship to customers, how many do they consider “good”?The former (some number of parts being bad) is considered “normal” in the IC industryMany factors cause a certain number of parts to be bad in every batchThe latter is what we are concerned about – how many parts that I ship are considered “bad”?Quality MetricsThe number of defective, shipped parts is normally expressed as “defective parts per million” or DPPMThe number of defective parts out of every lot of 1,000,000Some industries may require even higher rates of quality and use more stringent metrics, such as DPPBThought questions: How do you guarantee a certain DPPM rate? Does that mean you have to completely test every single part?Which is more expensive – a lot of testing or shipping some bad parts?These questions have no single right answer!Test Philosophy, ctd.Coming back to integrated circuits…So how do you test a single circuit?You have to apply every possible input and observe the correct output in every caseThere is no shortcut here – if you don’t do both, then there is the possibility that the circuit will not work under untested input conditionsThis drives two very important issues in testing:Controllability: Can you apply every single input case?Observability: Can you sense if the input is correct or not?Consider a simple example…2-input NOR gate:Apply all four input combinationsCheck the output for each casePiece of cake, right?But what if that gate is in the middle of a bunch of other logic?011001010100FBAABFConsider another example…Consider the following circuitABCDEFGWhat combinations of inputs and outputs test all 4 gates?Must apply every input combination and observe every output1234Consider another example…My answer…ABCDEFG12341111110010110000001000011011010100101100100000000GFEDCBAEach combinations of inputs and outputs is called a test vectorThis example has 7 vectorsGoal is to maximize coverage with minimal number of test vectorsNot-so-simple example…How do you control and observe every single gate in a complex circuit?For example, how do you apply all 4 combinations to the NOR gate above?How do you observe the output of all 4 input combinations?That may be impossible – the clock will cause the output to be non-observable ½ of the timeABFWe need a computer to keep track of it all!It soon becomes clear that we need special software tools to track every single transistorFind every instance where the output of the gate directly affects a measurable outputFind the input combination for that outputTrack how many input combinations have been applied and then observedThe overall result is the fraction of the chip that has been testedSimple example: 4 logic gates14/20 = 70% test coverage3441420Total683242341# actually tested# of possible combinationsGateHow good is “good enough”?Studies show how much testing is needed to achieve a certain level of reliabilitySource: sina.sharif.edu/~hessabi/Test/lec4.pdf 1000 DPPM = 99% coverage100 DPPM = 99.9% coverage10 DPPM = 99.99% coverageAnd so the problem emerges…If you want 10 to 100 DPPM (typical quality numbers), you need 99.9% to 99.99% test coverage.Example: 120,000,000 transistors = 30,000,000 gates = 120,000,000 input combinationsMust test about 119,880,000 out of 120,000,000 combinations to achieve 100 DPPMThe approach of simply applying inputs and checking outputs “runs out of gas” at around 90% - 95% test coverage.What shortcuts can we take?Eliminate input combinationsExample: Multiplier array (2-dimensional array of adders)Some combinations of inputs are physically impossible and can be eliminatedVery regular logic structuresExample: CountersMost input combinations are tested by exhaustively testing the states of the structureAside: The evil of counters…Counters are notorious in testability circlesExample: A 32-bit counter is only completely tested after a sequence of 232= 4 x 109iterationsClassic solution: Add logic to break a single big counter into several smaller countersExample: Break 32-bit counter into 4 8-bit countersSegues into the next step: Add testability logicTestability LogicIt soon becomes clear that extra logic will be needed just to finish the testingExample: Breaking up countersExample: Injecting number patterns into arithmetic logicExample: Observing internal logic states on outputsWhat if the testability logic is itself broken?Doesn’t really matter, as long as faults are manifested in observable waysYou cannot fix an IC – you only want to throw it away if it is broken – so it doesn’t matter if the testability logic is broken or the logic under test is brokenHow do we get controllability and observability?In general, digital circuits consist of patches of combination logic strung between flip-flopsIf you can control the flip-flops, you can force input combinations into the combinational logicIf you can observe the flip-flops, you can read the internal behaviors of the combinational logicCombinationalLogicclockOutputsStateRegistersNextStateCurrentStateInputsStateRegistersStateRegistersMethod 1: Built-in Self-Test (BIST)It is easy to build circuits that create repeatable bit patternsBuilt up from networks of XOR