EE534VLSI Design SystemSummer 2004Lecture 05: MOS Resistanceand Static CMOS inverterCMOS Inverter: DynamicVDDRnVout= 0Vin= VDDCLtpHL= f(Rn, CL)Last lecture’s focusToday’s focusTransient, or dynamic, response determines the maximum speed at which a device can be operated.Review: Sources of CapacitanceVoutCwVinCDB2CDB1CGD12M2M1M4M3Vout2CG4CG3wiring (interconnect) capacitanceintrinsic MOS transistor capacitancesVout2Vinextrinsic MOS transistor (fanout) capacitancesVoutCLSources of ResistanceMOS structure resistance - RonSource and drain resistanceContact (via) resistanceWiring resistanceTop viewDrain n+ Source n+WLPoly GateMOS Structure ResistanceThe simplest model assumes the transistor is a switch with an infinite “off” resistance and a finite “on” resistanceRonHowever Ronis nonlinear, so use instead the average value of the resistances, Req, at the end-points of the transition (VDDand VDD/2)Req= ½ (Ron(t1) + Ron(t2))SDRonVGS≥ VTEquivalent MOS Structure ResistanceFor VDD>>VT+VDSAT/2, Reqis independent of VDD (see plot). Only a minor improvement in Reqoccurs when VDDis increased (due to channel length modulation)Once the supply voltage approaches VT, Reqincreases dramatically313855115PMOS (kΩ)13151935NMOS(kΩ)2.521.51VDD(V)Req(for W/L = 1), for larger devices divide Reqby W/LVDD(V)Req(Ohm)x105(for VGS= VDD, VDS = VDD→VDD/2)012345670.5 1 1.5 2 2.5The on resistance is inversely proportional to W/L. Doubling W halves ReqSource and Drain ResistanceMore pronounced with scaling since junctions are shallowerWith silicidation Ris reduced to the range 1 to 4 Ω/RSRDSGDRS,D= (LS,D/W)R +RCwhere LS,D is the length of the source or drain diffusion Ris the sheet resistance per square of the source or drain diffusion (20 to 100 Ω/), Rc is contact resistanceContact ResistanceTransitions between routing layers (contacts through via’s) add extra resistance to a wire keep signals wires on a single layer whenever possible avoid excess contacts reduce contact resistance by making vias larger (beware of current crowding that puts a practical limit on the size of vias) or by using multiple minimum-size vias to make the contactTypical contact resistances, RC, (minimum-size) 5 to 20 Ω for metal or poly to n+, p+ diffusion and metal to poly 1 to 5 Ω for metal to metal contactsMore pronounced with scaling since contact openings are smallerWire ResistanceLWHR =ρ LH WSheet Resistance RR1R2==ρ LA=5.5 x 10-8Tungsten (W)2.7 x 10-8Aluminum (Al)2.2 x 10-8Gold (Au)1.7 x 10-8Copper (Cu)1.6 x 10-8Silver (Ag)ρρρρ(ΩΩΩΩ-m)Material0.05 to 0.1Aluminum4 to 5polysilicon with silicide150 to 200polysilicon3 to 5n+, p+ diffusion with silicide50 to 150n+, p+ diffusion1000 to 1500n, p well diffusionSheet Res. (ΩΩΩΩ/)MaterialSkin EffectAt high frequency, currents tend to flow primarily on the surface of a conductor with the current density falling off exponentially with depth into the wireHWδ= √(ρ/(πfµ))where f is frequencyµ = 4π x 10-7H/mso the overall cross section is ~ 2(W+H)δδ= 2.6 µmfor Al at 1 GHzThe onset of skin effect is at fs- where the skin depth is equal to half the largest dimension of the wire.fs= 4 ρ / (π µ (max(W,H))2)An issue for high frequency, wide (tall) wires (i.e., clocks!)Skin Effect for Different W’sA 30% increase in resistance is observe for 20 µm Al wires at 1 GHz (versus only a 1% increase for 1 µm wires)0.11101001000Frequency (Hz)% Increase in ResistanceW = 1 um W = 10 umW = 20 um1E8 1E9 1E10for H = .70 umThe Wireschematic physicaltransmittersreceiversWire ModelsAll-inclusive (C,R,l) model Capacitance-onlyInterconnect parasitics (capacitance, resistance, and inductance) reduce reliability affect performance and power consumptionParasitic SimplificationsInductive effects can be ignored if the resistance of the wire is substantial enough (as is the case for long Al wires with small cross section) if the rise and fall times of the applied signals are slow enoughWhen the wire is short, or the cross-section is large, or the interconnect material has low resistivity, a capacitance only model can be usedWhen the separation between neighboring wires is large, or when the wires run together for only a short distance, interwire capacitance can be ignored and all the parasitic capacitance can be modeled as capacitance to groundSimulated Wire Delays00.511.522.50 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5voltage (V0)time (nsec)VinVoutLL/10 L/4 L/2 LOvercoming Interconnect ResistanceSelective technology scaling scale W while holding H constantUse better interconnect materials lower resistivity materials like copper- As processes shrink, wires get shorter (reducing C) but they getcloser together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse.- Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner (reducing C) without increasing R use silicides (WSi2, TiSi2, PtSi2and TaSi)- Conductivity is 8-10 times better than poly alonen+n+SiO2polysiliconsilicidepUse more interconnect layers reduces the average wire length L (but beware of extra contacts)Wire Spacing ComparisonsIntel P856.5Al, 0.25µm Ω - 0.33 M2Ω - 0.33 M3Ω - 0.12 M4Ω - 1.11 M1Ω - 0.05 M5Scale: 2,160 nmΩ - 0.49 M2Ω - 0.49 M3Ω - 0.17 M4Ω - 1.00 M1Ω - 0.08 M5Ω - 0.07 M6Intel P858Al, 0.18µm IBM CMOS-8SCU, 0.18µmΩ - 0.97 M1Ω - 0.10 M6Ω - 0.10 M7Ω - 0.70 M2Ω - 0.50 M3Ω - 0.50 M4Ω - 0.50 M5From MPR, 2000Design Abstraction LevelsSYSTEMGATECIRCUITVoutVinCIRCUITVoutVinMODULE+DEVICEn+S Dn+GAt present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications.The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive.Although the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital circuits