EE534VLSI Design SystemLecture 10:Chapter 7Layout and Combinational MOS logic circuits design approachesReview: Construction of PDNNMOS devices in series implement a NAND functionNMOS devices in parallel implement a NOR functionABA • BA BA + BReview: Equivalent inverter: effective width to length ratios (model I)For the NOR gate the effective width of the drivers transistors doubles. That means the effective aspect ratio is increased.For the NAND gate the effective length of the driver transistors doubles. That means the effective aspect ratio is decreased..Parallel combinationSeries combinationReview: Equivalent inverter: Worse case delay design considerationRepresent complex gate as inverter for delay estimationUse worse-case delaysExample: NAND gateWorse-case (slowest) pull-up: only 1 PMOS “on”Pull-down: both NMOS “on”WNWNWPWPWP½ WNKPKn/2Review: CMOS NOR gate: design considerationABABnppTDDnpnTthKKVVkkVINRV+−+=1)()(,,nppTDDnpnTthKKVVkkVINRV41)(4)(,,+−+=nppTDDnpnTthKNKVVkNkVINRV2,2,1)()(+−+=Two inputFor N inputsOne inputWp/22WnKP/22KnTransistor sizing: an approachIf MOSFET serially connected in a current path, the overall current path resistance will beAll serially connected MOSFET can be replace with a single MOSFET asIf the MOSFET are connected in parallel combination then,+++=332211WLWLWLWLeqqe..1332211+++=LWLWLWWLeqqe..)(..332211332211=++=+++=WLWLWLRsRWRsLWRsLWRsLRReview: Stick DiagramsContains no dimensionsRepresents relative positions of transistorsInOutVDDGNDInverterAOutVDDGNDBNAND2Review: Dual Graph conceptCA BX = C • (A + B)BACijjVDDXXiGNDABCPUNPDNABCLogic GraphReview: CMOS gate layoutGoal: minimum areaMethodMinimize diffusion breaks (reduces capacitance on internal nodes)Align transistors with common gates above each other in layout (minimizes poly length)Group PMOS and NMOS transistors togetherApproach:Use Euler path method to find ordering of transistors in layoutReview: Complex CMOS logic gatesReview: Complex CMOS logic gates: Euler path methodReview: Layout: Euler path methodABCDEC EDBAEuler path: B→A→C→E→DB A C E DVccGndFF1. Order transistors gates according to Euler path2. Connect Vcc and Gnd3. Make other connections according to circuit diagramFan-In ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL]tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.tpas a Function of Fan-In0250500750100012502 4 6 8 10 12 14 16tpHLtpLHtp(psec)fan-inquadratic function of fan-inlinear function of fan-in Gates with a fan-in greater than 4 should be avoided.tptpas a Function of Fan-Out2 4 6 8 10 12 14 16tpNOR2tp(psec)eff. fan-outAll gates have the same drive current.tpNAND2tpINVSlope is a function of “driving strength”Influence of Fan-In and Fan-Out on DelayVDDABABCDC DFan-out: Number of Gates connected to the outputin static CMOS, there are two gate capacitances per Fan-outFan-in: Number of independent variables for the logic function, which has a quadratic effect on tpdue to:resistance increasingcapacitance increasingFOaFIaFIatp 3221++=tpas a Function of Fan-In and Fan-OutFan-in: quadratic due to increasing resistance and capacitanceFan-out: each additional fan-out gate adds two gate capacitances to CLtp= a1FI + a2FI2+ a3FOFast Complex Gates: Design Technique 1Transistor sizingas long as fan-out capacitance dominatesProgressive sizing:InNCLC3C2C1In1In2In3M1M2M3MNDistributed RC line:M1 > M2 > M3 > … > MNM1: Widest transistorM2: Slightly less wide……MN: MOSFET closest to output – smallest transistorCan reduce delay by more than 20%; decreasing gains as technology shrinksWhy does this work? Resistance of M1(R1) N times in the delay equation. Resistance of M2(R2) appears N-1 times etc. Fast Complex Gates: Design Technique 2Input re-orderingwhen not all inputs arrive at the same timeC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedSizing and Ordering EffectsDCBADCBACLC3C2C1Progressive sizing in pull-down chain gives up to a 23% improvement.Input ordering saves 5%critical path A – 23% 3 3 3 344444567= 100 fFFast Complex-Gate Design Techniques: Stages and Fan-in Considerations• Improved Logic DesignFast Complex Gates: Design Technique 3Alternative logic structuresF = ABCDEFGHFast Complex Gates: Design Technique 4Reducing the voltage swinglinear reduction in delayalso reduces power consumptiontpHL= 0.69 (CL VDD)/ IDSATn)= 0.69 (CL Vswing)/ IDSATn)CMOS disadvantagesFor N-input CMOS gate, 2N transistors requiredEach input connects to an NMOS and PMOS transistorLarge input capacitance: limits fanoutLarge fan-in gates: always have long transistor stack in PUN or PDNLimits pullup or pulldown delayRequires very large transistorsRatioed LogicRatioed logic is an attempt to reduceThe number of transistors required to implant a given logic function, often at the cost of reduced robustness and extra power dissipationRatioed LogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: to reduce the number of devices over complementary CMOSRatioed LogicVDDVSSPDNIn1In2In3FRLLoadResistiveN transistors + Load• VOH = VDD• VOL = RPNRPN + RL• Assymetrical response• Static power consumption•• tpL= 0.69 RLCLActive LoadsVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNDepletionLoadPMOSLoaddepletion load NMOS pseudo-NMOSVT < 0Pseudo-NMOS logicPseudo-NMOS: replace PMOS PUN with single “always-on” PMOS deviceSome problems as pseudo-NMOS inverter:VOLlarger than 0static power when PDN is onAdvantagesReplace large PMOS stacks with single deviceReduces overall gate size, input capacitanceEspecially useful for wide-NOR structuresPseudo-NMOSVDDA B C DFCLVOH = VDD (similar to complementary CMOS)knVDDVTn–( )VOLVOL22-------------–   kp2------ VDDVTp–( )2=VOLVDDVT–( )1 1kpkn------––(assuming that VTVTnVTp)= = =SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!≠0Overall functionality of the gates depend on the NMOS and PMOS sizePseudo-NMOS VTC0.0 0.5 1.0 1.5 2.0