EE534VLSI Design SystemLecture 11:Chapter 7&9Transmission gate andDynamic logic circuits design approachesReview: Fan-In ConsiderationsDCBADCBACLC3C2C1Distributed RC model(Elmore delay)TpHL=0.69[R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL]tpHL= 0.69 Reqn(C1+2C2+3C3+4CL)Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.Review: tpas a Function of Fan-In0250500750100012502 4 6 8 10 12 14 16tpHLtpLHtp(psec)fan-inquadratic function of fan-inlinear function of fan-in Gates with a fan-in greater than 4 should be avoided.tpReview: Influence of Fan-In and Fan-Out on DelayVDDABABCDC DFan-out: Number of Gates connected to the outputin static CMOS, there are two gate capacitances per Fan-outFan-in: Number of independent variables for the logic function, which has a quadratic effect on tpdue to:resistance increasingcapacitance increasingFOaFIaFIatp 3221++=Fast Complex Gates: Design Technique 1Transistor sizingas long as fan-out capacitance dominatesProgressive sizingInNCLC3C2C1In1In2In3M1M2M3MNDistributed RC lineM1 > M2 > M3 > … > MN(the MOSFET closest to the output should be the smallest)Can reduce delay by more than 20%; decreasing gains as technology shrinksResistance of M1(R1) N times in the delayEquation. The resistance of M2(R2) appears N-1 times etc. Review : Fast Complex Gates: Design Technique 2Input re-orderingwhen not all inputs arrive at the same timeC2C1In1In2In3M1M2M3CLC2C1In3In2In1M1M2M3CLcritical path critical pathcharged10→1chargedcharged1delay determined by time to discharge CL, C1and C2delay determined by time to discharge CL110→1chargeddischargeddischargedReview: Sizing and Ordering EffectsDCBADCBACLC3C2C1Progressive sizing in pull-down chain gives up to a 23% improvement.Input ordering saves 5%critical path A – 23% 3 3 3 344444567= 100 fFReview: Fast Complex Gates: Design Technique 3Alternative logic structuresF = ABCDEFGHReview: Ratioed LogicVDDVSSPDNIn1In2In3FRLLoadVDDVSSIn1In2In3FVDDVSSPDNIn1In2In3FVSSPDNResistiveDepletionLoadPMOSLoad(a) resistive load (b) depletion load NMOS (c) pseudo-NMOSVT < 0Goal: to reduce the number of devices over complementary CMOSReview: Load Lines of Ratioed Gates0.0 1.0 2.0 3.0 4.0 5.0Vout (V)00.250.50.751IL(Normalized)Resistive loadPseudo-NMOSDepletion loadCurrent sourceOther logic stylesTransmission gate logicPass-transistor logicNMOS transistors used as switchesOther variants:- Complementary pass-transistor logic (CPL)- Swing-restored pass-transistor logicTransmission Gate LogicNMOS and PMOS connected in parallelAllows full rail transition – ratioless logicEquivalent resistance relatively constant during transitionComplementary signals required for gatesSome gates can be efficiently implemented using transmission gate logic= =Transmission Gates (pass gates)Use of transistors as switches are called transmission gates because switches can transmit information from one circuit to another.CMOS Transmission GateA CMOS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals.The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation.CMOS transmission gateCharacteristics of a CMOS Transmission gateCase I:If φ =VDD, , VI=VDD, and VOis initially zero.In NMOS transistor, under above Condition, terminal ‘a’ acts as the drain and terminal ‘b’ acts as the source.For the PMOS, device terminal ‘c’ acts as the drain and terminal ‘d’ acts as the source. In order to charge the load capacitor, current enters the NMOS drain and the PMOS source. The NMOS gate to source voltage is,VGSN = φ - VO = VDD - VOthis implies that VGSNcontinuously changes.And for PMOS source-to-gate voltage isVGSP = VI - φ = VDD – 0 = VDDThis implies that VGSPremains constant.DrainsourcesourceDrain0=φCharging pathCharacteristics of a CMOS Transmission gate (Cont.)When VO=VDD-VTN, VGSN=VTN,the NMOS transmission gate cutsoff and IDN=0.However, PMOS transistor continues to conduct, because VGSPof the PMOS is a constant (VGSP=VDD). In PMOS transistorIDP=0, when VSDP=0, which would bepossible only, if,VO = VI = 5VDrainsourcesourceDrainDrainsourcesourceDrainThis implies that a logic ‘1’ is transmitted unattenuated throughthe CMOS transmission gate in contrast to the NMOS transmission gate.Characteristics of a CMOS Transmission gate (Cont.)Case II:IfVI= 0, φ = VDD, VO=VDDinitially.terminal ‘a’ acts as a source and terminal‘b’ acts as a drain.For the PMOS transistor terminal‘c’ acts as a source and terminal ‘d’ acts as a drain.In order to discharge the capacitors current enter the NMOS drain and PMOS source. The NMOS gate to source voltage is,And PMOS source to gate voltage isWhen VSGP=VO=|VTP|,PMOS transistor cuts off and iDP=oHowever, since VGSN=VDD, the NMOS transistor continuesconducting and capacitor completely discharge to zero. Finally, VO=0, which is a good logic 0.sourcedrainsourcedrainOOOSGPvvvv =−=−= 0φDDDDIGSNVvvv =−=−= 0φ0=φdischarging pathEquivalent Resistance ModelFor a rising transition at the output (step input)NMOS sat, PMOS sat until output reaches |VTP|NMOS sat, PMOS lin until output reaches VDD-VTNNMOS off, PMOS lin for the final VDD– VTNto VDDvoltage swingDrainsourcesourceDrainDrainsourcesourceDrainVinVoutVcc0VnDSoutDDneqIVVR,,−=pDSoutDDpeqIVVR,,−=Equivalent Resistance – Region 1NMOS sat:PMOS sat:()( )221,tnoutDDnoutDDneqVVVkVVR−−−=()( )221,tpDDpoutDDpeqVVkVVR−−−=DrainsourcesourceDrainDrainsourcesourceDrainNMOS sat, PMOS sat until output reaches |VTP| because drain to source voltage is still highEquivalent Resistance – Region 2NMOS sat:PMOS lin:()( )( ) ( )( )( )( )[ ]outDDTPDDpoutDDoutDDTPDDpoutDDpeqVVVVkVVVVVVkVVR−−−=−−−−−=21221,1()( )221,tnoutDDnoutDDneqVVVkVVR−−−=DrainsourcesourceDrainDrainsourcesourceDrainNMOS sat, PMOS lin until output reaches VDD-VTNEquivalent Resistance – Region 3NMOS off:PMOS lin:∞∞∞∞====neqR,( )( )[ ]outDDTPDDppeqVVVVkR−−−=21,1DrainsourcesourceDrainDrainsourcesourceDrainNMOS off, PMOS lin for the final VCC– VTNto VCCvoltage swingEquivalent resistanceEquivalent resistance Reqis parallel combinaton of Req,nand Req,pReqis