EE534VLSI Design SystemLecture 6: Static CMOS Inverter:Switching Behavior(CHAPTER 6)Review: CMOS inverter design considerationThe CMOS inverter usually design to have, (i) VTN=|VTP|(ii) K´n(W/L)=K´p(W/L)But K´n> K´p(because µn>µp)How equation (ii) can be satisfied?This can be achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.Review: Noise margin calculationsVout= VDSDrain current IDSVin=2VVCCVin=1VVin=3VVin=4VNML=VIL-VOL(noise margin for low input)NMH=VOH-VIH(noise margin for high input)Review: CMOS inverter: VILand VIHfor Ideal VTH(Symmetrical, Kn=Kp)Assuming VT0,n=-VT0,p, and kR= 1,()02381TCCILVVV+=( )02581TCCIHVVV −=(symmetrical inverter)RnTRCCpToutILkVkVVVV++−+=12,0,0()RnToutRpTCCIHkVVkVVV++++=12,0,0(asymmetrical inverter)NML=VIL-VOL(noise margin for low input)NMH=VOH-VIH(noise margin for high input)Review: CMOS inverter: VTHKCL:Solve for VTH= Vin= Vout( )( )2,0,2,0,22pTpGSpnTnGSnVVkVVk−=−( )( )2,02,022pTCCinpnTinnVVVkVVk−−=−( )RpTCCRnTTHkVVkVV111,0,0+++=pnRkkk =Chapter 6Switching Characteristics of CMOS inverter(Dynamic characteristics)Delay DefinitionstVoutVininputwaveformoutputwaveformtp= (tpHL+ tpLH)/2Propagation delayt50%tpHL50%tpLHtf90%10%trsignal slopesVinVoutThe propagation delay tpof a gate defines how quicklyit responds to a change at its input(s).Inverter Transient Response (input step pulse)-0.500.511.522.530 0.5 1 1.5 2 2.5VinVout(V)t (sec) x 10-10 VDD=2.5V0.25µmW/Ln= 1.5W/Lp= 4.5Reqn= 13 kΩ (÷ 1.5)Reqp= 31 kΩ (÷ 4.5)tpHL= 36 psectpLH= 29 psecsotp= 32.5 psectftrtpHLtpLHFrom simulation: tpHL= 39.9 psec and tpLH= 31.7 psecInverter delay, fallingAssume PMOS fully off (ID,p= 0)CloadVinID.n∫====nDoutloadoutloadoutloadnDIdVCtIdVCdtdtdVCIdtdVCInD,,,Need to determine ID,nVinVoutCloadCalculation of Delay times: Average current methodHLavgOHloadHLavgHLloadPHLIVVCIVC,)(,.%50−=∆=τLHavgOLloadLHavgLHloadPLHIVVCIVC,)(,.%50−=∆=τThe average current during high to low transition can be calculated by using the current values at the beginning and the end of the transition.[ ]),(),(21,%50VVVVIVVVVinIIoutOHinCOHoutOHCHLavg==+===[ ]),(),(21,%50 OLoutOLinCoutOLinCLHavgVVVVIVVVVII ==+===The average current during low to high transition can be calculated by using the current values at the beginning and the end of the transition.Inverter delay: Differential equation methodFrom t0to t1: NMOS in saturationFrom t1to t2: NMOS in linear regionFind IDin each regionVcc(VOH)Vcc – VT,nV50%(Vcc/2)t0t1t2NMOS in saturationNMOS in linear regionThe following derivations were made under the simplifying assumption that the input signal waveform is a step pulse with zerorise and fall times.Later we’ll see how to take non-zero input rise and fall times into account.Inverter delay, falling t1-t0Assumption: Input fast enough to go through transition before output voltage changes: Vin= VOHinstantaneouslyVoutdrops from VOHto VCC-VTN(NMOS saturation / linear boundary)2,0,0012,02,02,0)(2)(22/)(2/)(,010nTOHnnTLVVVoutnTOHnLttnTOHnnTinnDSVVkVCttdVVVkCdtVVkVVkInTOHOH−=−−−=−=−=∫∫−Inverter delay, falling t2-t1Voutdrops from (VOH-VT0,n) to V50%= (VOH+ VOL) / 2Why V50%? That is the definition of τPHL!So, with the NMOS in the linear region…[][ ]++−−−=−−−−−=−−−−=−−−==−==−∫2/)(2/)()(2ln)()(2ln)()(22)(22,0,012,0,0122,0122,0%50,0%50,0OLOHOLOHnTOHnTOHnLVVVVVoutnTOHoutnTOHnLVVVVoutoutnTOHnoutLoutoutnTOHnDSVVVVVVVVkCttVVVVVVkCttVVVVkdVCttVVVVkIoutnTOHoutoutnTOH−=−−=−∫xaxaaaxxdxxaxln1)ln()ln()(1Inverter delay, fallingTotal fall delay =(t1-t0) + (t2-t1)−+−+−−= 1)(4ln2)(,0,0,0,0 OLOHnTOHnTOHnTnTOHnLPHLVVVVVVVVVkCtInverter delay, risingSimilar calculation as for falling delaySeparate into regions where PMOS is in linear, saturation−+−−+−−−−= 1)(4ln2)(,0,0,0,0OLOHpTOLOHpTOLOHpTpTOLOHpLPLHVVVVVVVVVVVVkCtDelay Definitions, ReprisetVoutVininputwaveformoutputwaveformtp= (tpHL+ tpLH)/2Propagation delayt50%tpHL50%tpLHtf90%10%trsignal slopesVinVoutThe propagation delay tpof a gate defines how quicklyit responds to a change at its input(s).Inverter rise, fall time: approaches Exact method: separate into regionst1- Voutdrops from 0.9VCCto VCC-VT(NMOS in saturation)- Voutrises from 0.1VCCto VT(PMOS in saturation)t2- Voutdrops from VCC-VTto 0.1VCC(NMOS in linear region)- Voutrises from VTto 0.9 VCC(PMOS in linear region)tf,r= t1+ t2Average current method:Find current at start and end of transitionFind average and use avgrisefallIVC∆=,τExample 6.2CMOS inverter actual delayWhat if input has non-zero rise/fall time?⇒not a step pulseBoth transistors are on for some amount of timeCapacitor charge/discharge current is reduced222)()(+=rphlphltinputsteptactualt222)()(+=fplhplhtinputsteptactualtEmpirical equations:Empirical equations of this form are often used to “combine” rise and fall timesExample :6.3Vdd=3.3V, Ln=Lp=0.8µm, Cin=100fF, Wp/Wn=2.75CMOS design simulation resultsThe smallest transistor has largest propagation delay (why?)Propagation delay simulation resultsAt large channel width, the delay approaches a limit value of about 0.2 ns, which is mainly determined by technology-specific parameters, independent of extrinsic capacitance component. The gain in drive strength is offset by theIncrease in overall capacitance, so there is little net improvement in delay.Inverter delay revisited (Lower VddIncreases Delay) CL * VddI=TdTd(Vdd=5)Td(Vdd=2)= (2) * (5 - 0.7)2(5) * (2 - 0.7)2≈4I ~ (Vdd - Vt)2Relatively independent of logic function and style.1.001.502.002.503.003.504.004.505.005.506.006.507.007.502.00 4.00 6.00Vdd (volts)NORMALIZED DELAY adder (SPICE)microcoded DSP chipmultiplieradder ring oscillatorclock generator2.0µm