Week 14a Micro and Nanotechnology 1 Some preliminaries a End of the propagation delay story b Silicon Run video CMOS discussion if time c Just for fun Hop On Board Microlab safety video if time d Energy Band View of Semiconductors if time shortened version of notes handed out earlier e Some electronic application examples if time 2 Micro and Nanotechnology introduction 1 The sizes of things 2 Some micromachines 3 A bit about nanotech 3 What about radio Week 14a Fall 2005 EE42 100 Prof White 1 1a Propagation delay in logic circuits Week 14a Fall 2005 EE42 100 Prof White 2 TIMING DIAGRAMS Show transitions of variables vs time A B Logic state D A B C C t 0 B Note B becomes valid one gate delay after B switches t D Note that becomes valid two B C B C switch gate delays after because the invert function takes one delay and the NAND function a second No change at t 3 D Week 14a Fall 2005 B C t D 2 D A B t D D EE42 100 Prof White D 2 D3 D t 3 WHAT IS THE ORIGIN OF GATE DELAY Logic gates are electronic circuits that process electrical signals Most common signal for logic variable voltage Specific voltage ranges correspond to 0 or 1 Volts 3 2 1 0 Range 1 Thus delay in voltage rise or fall because of delay in charging internal capacitances will translate to a delay in signal timing Gray area not allowed Range 0 Note that the specific voltage range for 0 or 1 depends on logic family and in general decreases with logic generations Week 14a Fall 2005 EE42 100 Prof White 4 VOLTAGE WAVEFORMS TIME FUNCTIONS Inverter input is v t output is v t IN OUT inside a large system v IN t v OUT t Vin t t Week 14a Fall 2005 EE42 100 Prof White 5 GATE DELAY PROPAGATION DELAY Define as the delay required for the output voltage to reach 50 of its final value In this example we will use 3V logic so halfway point is 1 5V Inverters are designed so that the gate delay is symmetrical rise and fall Vin t 1 5 t Vout t Approximation 1 5 Week 14a Fall 2005 D EE42 100 DWhite D Prof t 6 WHAT DETERMINES GATE DELAY Example The gate delay is simply the charging of the capacitors at internal nodes Oversimplified example using ideal inverter II v OUT t and 5V logic swing v OUT t v IN t v IN t RC 0 1ns 5 R Vx C MODEL v OUT t II vIN RC 0 1ns so 0 069ns after vIN switches by 5V Vx moves 2 5V Week 14a Fall 2005 EE42 100 Prof White 2 5 v IN t 5 2 5 Vx vOUT D 0 069ns 7 t Controlled Switch Model of Inverter VDD 2V SP is closed if VIN VDD SP RP VIN VOUT RN Input SN SN is closed if Output VIN VSS VSS 0V So if VIN is 2V then SN is closed and SP is open Hence VOUT is zero But if VIN is 0V then SP is closed and SN is open Hence VOUT is 2V Week 14a Fall 2005 EE42 100 Prof White 8 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays use 35 for calculations Implication if clock frequency 500 MHz clock period 5 108 s 1 1 Period 2 10 9s 2 ns nanoseconds Gate delay must be D 1 35 Period 2 ns 35 57 ps picoseconds How fast is this Speed of light c 3 108 m s Distance traveled in 57 ps is CX D 3x108m s 57x10 12 17 x 10 4 m 1 7cm Week 14a Fall 2005 EE42 100 Prof White 9 1d Energy Band View of Semiconductors Conductors semiconductors insulators Why is it that when individual atoms get close together to form a solid such as copper silicon or quartz they form materials that have a high variable or low ability to conduct current Understand in terms of allowed empty and occupied electronic energy levels and electronic energy bands Fig 1 shows the calculated allowed energy levels for electrons vertical axis versus distance between atoms horizontal axis for materials like silicon Week 14a Fall 2005 EE42 100 Prof White 10 Fig 1 Calculated energy levels in the diamond structure as a function of assumed atomic spacing at T 0o K From Week 14a Fall 2005 EE42 100 Prof White Introduction to Semiconductor Physics Wiley 1964 11 In Fig 1 at right atoms are essentially isolated at left atomic separations are just a few tenths of a nanometer characteristic of atoms in a silicon crystal If we start with N atoms of silicon at the right which have 14 electrons each there must be 14N allowed energy levels for the electrons You learned about this in physics in connection with the Bohr atom the Pauli Exclusion principle etc If the atoms are pushed together to form a solid chunk of silicon the electrons of neighboring atoms will interact and the allowed energy levels will broaden into energy bands Week 14a Fall 2005 EE42 100 Prof White 12 When the actual spacing is reached the quantum mechanical calculation results are that at lowest energies very narrow ranges of energy are allowed for inner electrons these are core electrons near the nuclei a higher band of 4N allowed states exists that at 0oK is filled with 4N electrons then an energy gap EG appears with no allowed states no electrons permitted and at highest energies a band of allowed states appears that is entirely empty at 0oK Can this crystal conduct electricity EE42 100 Prof White Week 14a Fall 2005 13 NO it cannot conductor electricity at 0o K because that involves moving charges and therefore an increase of electron energy but we have only two bands of states separated by a forbidden energy gap EG The lower valence band is entirely filled and the upper conduction band states are entirely empty To conduct electricity we need to have a band that has some filled states some electrons and some empty states that can be occupied by electrons whose energies increase Week 14a Fall 2005 EE42 100 Prof White 14 Metals pure silicon at 0K and 300K and doped silicon A Conductors such as aluminum and gold can conduct at low temperatures because the highest energy band is only partly filled there are electrons and there are empty states they can move into when caused to move by an applied electric field B Silicon at 0K can t conduct because the highest band containing electrons is filled C Pure silicon at room temp is slightly conductive since thermal energy can raise some electrons to the mostly empty conduction band D Silicon doped with donors like P or As can conduct and Become n type better than pure silicon at room temp since it doesn t take much energy to free a valence electron so it can …
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