San Jos State University Charles W Davidson College of Engineering DEPARTMENT OF ELECTRICAL ENGINEERING EE271 Advanced Digital System Design and Synthesis Instructor Prof Thuy T Le Office Location Engineering Building room 369 Telephone 408 924 5708 Fax 408 924 3925 Email Thuy Le sjsu edu Web Page www engr sjsu edu tle Office Hours Monday Wednesday 15 00 17 30 Class Days Time Monday Wednesday 18 00 19 15 Classroom Engineering Building room 345 Prerequisites EE270 Advanced Logic Design or equivalent experience Background in integrated circuit design is helpful Must have self motivations in learning EDA tools and Verilog HDL Faculty Web Page Course information and materials such as course syllabus tutorials journal proceeding papers homework lab assignments and solutions office hours special announcements etc will be posted on my web page at www engr sjsu edu tle Students are responsible for regularly checking the web page for the information Course Description This course covers topics in the advanced design and analysis of digital circuits with HDL The primary goal is to provide in depth understanding of logic and system design synthesis and optimization for area speed and power consumption The course enables students to apply their knowledge for the design of advanced digital hardware systems with corresponding EDA tools Verilog HDL will be used for simulation and synthesis of the homework assignments and final design project Student Learning Objectives Upon successful completion of this course students will be able to LO1 Design and manually optimize complex combinational and sequential digital circuits LO2 Model combinational and sequential digital circuits by Verilog HDL LO3 Design and model digital circuits with Verilog HDL at behavioral structural and RTL levels EE271 Advanced Digital System Design and Synthesis Fall 2009 Page 1 of 7 Do not consume food in the classroom LO4 LO5 LO6 LO7 LO8 Develop testbenches to simulate combinational and sequential circuits Perform functional and timing verifications of digital circuits Perform static and dynamic timing analysis with false paths and hazards Synthesis combinational and sequential circuits with trade offs in timing area and power Improve timing performance of a digital circuit by using pipelining and superscalar techniques LO9 Design various advanced high speed digital arithmetic circuits including addition subtraction multiplication and division of integer fraction unsigned signed and floating point numbers in various number systems LO10 Estimate area and timing delay of various arithmetic circuits based on various implementation algorithms LO11 Estimate power distribution and power consumption of digital circuits Required Texts Readings and EDA Tools Textbooks EE271 Lecture Notes by Thuy T Le Each chapter will be posted on the class website two weeks before the start of the lecture and will be deleted once the lecture discussion is started in class Computer Arithmetic by David Goldberg Xerox Palo Alto Research Center Appendix A of Computer Architecture A Quantitative Approach by John L Hennessy David A Patterson Morgan Kaufmann Publishers Inc available on class website Additional Readings optional Any Verilog Language books notes Below are few on line documents http www doulos com knowhow verilog designers guide http www sutherland hdl com online verilog ref guide vlog ref top html Self research of additional reading materials based on topics covered in lecture notes EDA Tools Synopsys VCS required Available on SJSU Cadence Lab Synopsys Design Compiler synthesis tool required Available on SJSU Cadence Lab Silos optional Available on class website Any other Verilog simulator such as ModelSim PE optional Can be downloaded at www model com downloads evaluations asp UNIX Accounts on Cadence Laboratory Rooms E289 and E291 are Cadence laboratories installed with Cadence and Synopsys software tools Each registered SJSU student should automatically have a UNIX account If you do not know your login name and password or having problems with the account you can find out at https unix engr sjsu edu wiki doku php For Unix tutorial materials and other documents related to Cadence laboratory please consult Prof Parent s website at http www engr sjsu edu dparent EE271 Advanced Digital System Design and Synthesis Fall 2009 Page 2 of 7 Do not consume food in the classroom Classroom Protocol EE271 students understand that professional attitude is necessary to maintain a comfortable academic environment in the classroom For examples Students will put their cell phones in quiet vibration mode during the lecture Students understand that drinking water juices etc during the lecture is acceptable but NOT eating Students will not skip the lecture and then ask the instructor to summarize the lecture later on Office hours are for students to have questions not for the instructor to summarize the lecture for any specific student Students will come to the class on time and leave the class at the end of the lecture Students will consult the course syllabus for class policies and requirements before requesting the instructor for any special considerations and or exceptions To minimize possible tension during the exams students are requested to follow the exam rules closely Students will work on the project and report by their own and will not share the work with other students Students understand that long term learning is their responsibility and will always keep it up If you need to communicate with me please try to see me in person during the office hours If you must send me an email please clearly specify your full name course section etc I will not respond to email that I do not know the author or emails that have no manners Dropping and Adding Policies and Procedures Students are responsible for understanding the policies and procedures about add drops academic renewal etc Information on add drops are available at http info sjsu edu webdbgen narr soc fall Information about late drop is available at http www sjsu edu sac policies latedrops policy Students should be aware of the current deadlines and penalties for adding and dropping classes Assignments and Grading Policy Lectures The course will follow the selected subjects as listed on the course description Additional theory and examples will be given and discussed in class as much as time permits Please note that lecture materials are NOT solely based on the required text and so students are