Final Project ReportOnModeling and Simulation of High-Speed Digital Subscriber LineGeneration 2 (HDSL2) ModemsUsing PtolemySultan AhmedGeorge BenavidesKhalid IslamMay 8, 1998EE382C: Embedded Software SystemsSpring 1998Prof. Brian L. EvansDepartment of Electrical and Computer EngineeringThe University of Texas at AustinAbstract: The emerging HDSL2 standard promises reliable, low-cost, high-speed digital communicationsfor telecommuting, home office transactions, enterprise computing, internet access, and video conferencingover the existing telephone network. This technology is slated to offer two-way data communication at aspeed of 1.544 Mbps over a single twisted pair copper wire. This capacity far exceeds existing voice bandmaximum limit of 64 Kbps and ISDN limit of 144 Kbps and is comparable to that of T1 lines at a muchlower cost.We implemented a fully configurable HDSL2 modem in Ptolemy with the purpose of enabling tradeoffanalysis. This will allow the HDSL2 standards committee members to vary the key parameters thatsignificantly affect the complexity and memory requirement of the proposed standards. Theserequirements will help determine the feasibility of a single DSP chip solution.11. IntroductionHDSL2 is a high-speed data transmission protocol using existing single-paircopper telephone lines. It is designed to transmit and receive data at speeds of over 1.5Mbps. Our project goal was to model a fully configurable HDSL2 modem in Ptolemy.We chose the synchronous data flow (SDF) domain for, since it was adequate formodeling the HDSL2 modules.The key value or innovation in this project is to allow key parameters of thecomputationally intensive modules, such as the Trellis decoder and the Tomlinson-Harashima precoder (THP), to be varied at run time. This feature is intended to allowdynamic analysis of the HDSL2 standards, which are continually changing. The use ofthis dynamic implementation helps determine efficiency and feasibility of the standardsthat ultimately will require a Digital Signal Processor (DSP) chip solution.2. ModelingThe entire HDSL2 modem is a system, which requires significant signalprocessing. Therefore, the SDF domain is our choice for modeling. Some issues ofpossible BDF were considered since the modem does require retraining. This retrainingrequires a select BDF actor to switch between certain actors in the THP implementation(see section 3.4 for more details). However, if the standards committee requires periodicretraining (i.e. retrain the THP filter every certain period of time) then this behavior canbe model as SDF. Other issues pertain to the few cases of multi-rate that are needed forthe serial to parallel conversion, Trellis encoding and Trellis decoding. Although thecyclo-static SDF domain does well in reducing unneeded computation [1], theseadvantages are unnecessary for HDSL2. The SDF domain easily models these multi-rate2conversions with little overhead in memory and computation.3. Implementation3.1 Simple ModulesFigure 1 shows the block diagram of our HDSL2 implementation. There areseveral fairly simple blocks in this diagram that together require minimal computation.These are the framer, scrambler, serial to parallel converter, the bit to symbol mapper inthe transmitter section, and their corresponding blocks in the receiver section. Theseblocks map directly to SDF stars. Programmable parameters in these blocks are notneeded since the area of interest is in the coding schemes.11010bitsDeScramblertrellis_encoderScramblerXMgraphHDSL2FramerAddIIDGaussianTrellisDecoderHDSL2Unframer SymbolToBitConverterthp_tinputtapinDFEinputerroroutcfoutthp_invQuantTrainerTrainerForkFigure 1. Our implementation in Ptolemy.3.2 Trellis EncoderOur Trellis encoder takes the least significant bit from a 3-bit value and producestwo bits [2]. The two most significant bits of the 3-bit value are unaffected. Thus, thenet effect of encoding is to produce a 4-bit quantity of which the least significant 2 bitsare encoded. Our encoder is programmable. The user specifies the number of delays viaparameters, which relates to the number of states, and the equations for each of the two3encoded bits. The equations are passed in as a one-dimensional array of bits with 0 and 1corresponding respectively to the absence or presence of a particular delayed value.3.3 Trellis DecoderThis decoder is the most computation and memory intensive module. It accountsfor the majority of the total computation in the current HDSL2 proposal. Consequently,this algorithm is where most of the optimization effort via user programming is focused.We implemented a fully programmable Trellis decoder using the Viterbi algorithm. Thenumber of delays and the equations for the outputs are specified by the user. The decoderimplements a maximum-likelihood (ML) “soft” decoding scheme, which maximizes theprobability of recovering the transmitted data by combining the quantization stage withthe decoding [2].The programmability is achieved by dynamically allocating the data arrays forstoring the Trellis diagram information [2]. The size of the diagram grows exponentially(power of 2) with respect to the number of delays. Clearly, this is the key target foroptimization since reducing delays by one reduces the complexity by a factor of 2.Figure 2 below shows how such a diagram is constructed for 2 states. The HDSL2current proposal calls for a 512-state Trellis code [4]. Starting at a particular state (node)it is possible to transition to one of two states, depending on whether a 1 or a 0 bit input.Each transition has an associated output, which is compared to the actual value receivedby the decoder in order to compute the weight of the transition.4Figure 2: Trellis diagram for a two state Trellis code [1]The accuracy of the decoder depends on another parameter called prune depth.To retrive the most likely decoded values, the Trellis diagram must be allowed to grow.For infinite input streams, this means an infinitely long Trellis diagram. The decodedvalues are output only after the last bit is received. In a practical implementation, theTrellis diagram is only allowed to grow to have a length equal to the prune depth. If theprune depth is sufficiently big, the decoder will perform very close to its maximalpotential. The size of prune depth affects the memory requirement of the Trellis decoderlinearly.3.4 Tomlinson-Harashima PrecoderThe THP is an innovative design, which pre-filters the