AbstractCycle Domain Simulator for Phase-Locked LoopsNorman JamesDecember 1999As computers become faster and more complex, clock synthesis becomes critical.Due to the relatively slower bus clocks compared to the processor, it is necessary to usephase-locked loops (PLL) for multiplication and phase aligning of the clocks.A PLL is composed of both digital and analog components and is not modeledwell in a design environment for digital systems. There are design tools available that aremore adept for doing PLL simulations; however, they can be very costly and are still notsuitable for the way PLL’s are used in computer systems. While the literature surveydiscussed current methods for simulation, the goal of this project is to introduce a newsimulator that is specifically designed for simulating PLL’s used in computer systems.2INTRODUCTIONPhase-locked loops (PLL’s) are used in synchronous computer systemsthroughout the clock distribution to multiply and phase align the primary clocks. Theycan be arranged in series or parallel and can be on a separate chip or integrated intoanother chip. The computer as a synchronous system implies that each replicated(synthesized) clock has a known phase and frequency relationship to its reference. Thismakes the phase relationship (phase error) an important parameter in chip-to-chipcommunication. Also since chips have an upper frequency limit to which they operate,knowing the frequency distribution is imperative. These phase and frequency errors areknown as jitter. Jitter is the main parameter that any simulator should be able to predict.There are several different simulators used in industry for PLL simulations, eachone having its advantages and disadvantages. Traditionally, PLL’s implemented on a chip(microprocessor, digital signal processor, ASIC, clock chip, etc.) are modeled withgeneral purpose simulators such as SPICE. Other simulators include EESof, Matlab, andanalytical/behavioral models. The main aspects that make a PLL difficult to simulate areas follows:• Two sources of feedback – main feedback (“loop” in phase-locked loop) andoscillator feedback• High frequency clocks in conjunction with low frequency time constants• Picosecond accuracy• Digital components mixed with analog components (mixed-mode)• Digital – phase detector, frequency divider• Analog – voltage-controlled oscillator (VCO), charge pump, loop filterA PLL simulator should:• Run fast• Model CMOS processes• Predict jitter (clock stability)• Predict lock range (frequency range over which the PLL will lock)3PhaseFrequencyDetectorChargePumpupdownLoopFilterVCOFrequencyDividerfeedbackrefClock Distribution Figure 1: Phase-Locked Loop Block DiagramThis project introduces a simulator, known as CycleSim, that meets the outlinedspecifications and gives the designer a new tool for PLL applications. The report willfirst present a brief overview of PLL operation. Then CycleSim’s operation is discussedand finally simulation results are presented.PLL OVERVIEWIn general, a PLL used in computer systems is called a charge-pumped PLL and ismade up of the following components: phase-frequency detector (PFD), charge pump,loop filter, voltage-controlled oscillator (VCO), and frequency divider. The basic blockdiagram is shown in Figure 1.Essentially, a reference clock is driven into one input of the PFD and a feedbackclock is fed into the other input. The PFD outputs an up or down pulse depending onwhether the feedback is leading or lagging the reference. The up and down pulses areproportional to the difference in phase of the two clocks. The pulses are translated intocurrent by the charge pump, which either forces current into or out of the loop filter. Abasic loop filter integrates the current and generates a voltage which is the control for the4VCO. If the PFD is generating up pulses, the control voltage is “pumped” up causing thefrequency of the VCO to increase. The frequency divider, divides the VCO output by thedesired bus to chip multiplication factor.CYCLESIM OVERVIEWCycleSim is written in ANSI C++ and has been compiled under Windows NT andAIX. The simulator is neither a time-domain or frequency-domain simulator. It is acycle-domain simulator. The basic premise is that if a PLL were considered a black boxwith one input and one output, both input and output would be clocks and the onlysignificant aspect of these clocks is the period and phase. The amplitude aspects are ofno importance since we are primarily concerned with the phase and frequency accuracyof the clock.The simulator stores and works on rising edges only. This is equivalent to takinga sampled clock (from a simulator or hardware) and extracting the zero-crossing pointswhich are essentially the points in time at which the waveform rises through somethreshold (typically the midpoint). These points in time are referred to as time tags forthe purposes of this report. To illustrate the nature of the time tags, Figure 2 is a plot ofSimulation Iterations vs. Time Tags for clocks where one clock is three times faster thanthe other clock.CycleSim has no notion of a time step size. For each iteration, the time tags forthe multiple nodes are adjusted. For example, a simple simulation would contain threetime tagged nodes, the reference clock, the VCO output, and a divider output. Since thereference frequency is fixed, the time tags simply increase each iteration by the period.The VCO is more complicated in that its period is constantly being adjusted by power5Figure 2: Time Tags illustration showing two clocks with a 3:1 frequency ratiosupply noise, the control voltage, and a feedfoward current port. The divider is simplebecause it just changes the period of the incoming time tags by the desired divider setting.The only circuit issues the simulator cares about are ones that adjust the time tags andthat the time tags can easily be mapped into the time domain.SIMULATION RESULTSSimulation SpeedThe simulations are several orders of magnitude faster than time-domainsimulators such as SPICE. For 25,000 cycles, the simulator takes < 5 seconds tocomplete on a Pentium 133. Even scaled to slowest processors, the performance is stillreasonable. Also, the number of data points created is the number of cycles times thenumber of nodes. Table 1 is a comparison of SPICE and CycleSim for a PLL simulation.6SPICE CycleSimSimulation time (hours)120 41Number of data points(output