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UT EE 382C - Typical Embedded Signal Processing System

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THE UNIVERSITY OF TEXAS AT AUSTINTypical Embedded Signal Processing Systemcontrol panelASICmicrocontrollerreal-timeoperatingsystemcontrollerprocessuser interfaceprocesssystem busDSPassemblycodeprogrammableDSPhost portmemory interfaceprogrammableDSPhost portmemory interfacedual-ported memoryCODECDSPassemblycodeanaloginterfaceTHE UNIVERSITY OF TEXAS AT AUSTINHeterogeneity in System-Level DesignFSMdiscreteeventcosimulationlogicmodelcosimulationexecutionmodelsystem-level modelingsynthesisdetail modeling and simulationASICmodelexecutionmodelASICsynthesissoftwaresynthesispartitioningcompilerlogicsynthesissymbolicimperative dataflowTHE UNIVERSITY OF TEXAS AT AUSTINPtolemy ProjectDesign Methodologies for Heterogeneous Systems• Formal models of computation• Hierarchical compositions of modelsform complex systems• Synthesis and partitioning algorithms• Laboratory to test design methodologyis the Ptolemy software environmentPersonnel• Directors: Profs. Edward Lee and David Messerschmitt• Staff: 4 post-doctoral, 1 software manager, 2 administrative• Students: 13 graduate and 3 undergraduateClaudius PtolemaeusTHE UNIVERSITY OF TEXAS AT AUSTINHierarchical Graphs As Underlying Abstract SyntaxAttach semanticsFiniteStateMachineDataflowDiscrete-EventTHE UNIVERSITY OF TEXAS AT AUSTINComputational Models (Domains) in PtolemySDFDDFBDFCPDEC5600096000SilageVHDLCGPtolemyKernelMDSDFSprocPNVHDLBsynchronous dataflowdynamic dataflowmultidimensionalBoolean dataflowdiscrete-eventintegrated proc./understandingprocess networksCode generation domainsIPUSFSMfinite state machinecommunicatingprocessessynchronous dataflowtimeduntimedcontrolof signalsTHE UNIVERSITY OF TEXAS AT AUSTINHeterogeneous System-Level Design in PtolemyMultiple models of computation may be used in thesame system. Here, dataflow is used for signalprocessing, while a timed discrete-event systemmodels a communication network.Mixing Models• ATM network withthree 4x4 switches• Detailed model ofeach switch withqueueing and routingprotocols.• Dummy traffic(Poisson arrivals) tocreate congestion.• Test traffic (video andaudio) to measuresubjectiveperformance.THE UNIVERSITY OF TEXAS AT AUSTINOpen Research Issues in System-Level DesignTopic ExampleSpecificationIntegrated documentation Parameter relationshipsSystem optimization System rearrangementConverting graphical specificationsinto block diagramsMultidimensional compressionsystemsOptimizing algebraic specificationswith conversion into block diagramsAnalog filter designSimulationModels of computation Multidimensional dataflowCosimulation of diverse modelsof computationMixed signalCosimulation of diverseimplementation technologiesDSP coreSynthesisPartitioning Hardware/software codesignScheduling Minimizing data memory inDSP assembly code


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UT EE 382C - Typical Embedded Signal Processing System

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