AbstractCycle Domain Simulator for Phase-Locked LoopsNorman JamesOctober 1999As computers become faster and more complex, clock synthesis becomes critical.Due to the relatively slower bus clocks compared to the processor, it is necessary to usephase-locked loops (PLL’s) for frequency multiplication and phase alignment of theclocks.A computer design environment focuses mainly on digital design. A PLL beingcomposed of both digital and analog components does not match this type of designenvironment. Available design tools such as SPICE are adept at PLL simulations;however, they require long simulation time and are not well suited to the ways PLL’s areused in computer systems. This literature survey explores current ways of simulatingPLL’s, and gives the foundation for developing a simulator that is specifically designedfor PLL’s.2INTRODUCTIONTraditionally, phase-locked loops (PLL’s) implemented on a chip(microprocessor, DSP, ASIC, clock chip, etc.) are modeled with general-purposesimulators such as SPICE. PLL’s are used in synchronous computer systems throughoutthe clock distribution to frequency multiply and phase align the primary clocks. Theycan be arranged in series or parallel and can be on a separate chip or integrated intoanother chip. The computer as a synchronous system implies that each replicated(synthesized) clock has a known phase and frequency relationship to its reference. Thismakes the phase relationship (phase error) an important parameter in chip-to-chipcommunication. Also since chips have an upper frequency limit to which they operate,knowing the frequency distribution is imperative. These phase and frequency errors areknown as jitter. Jitter is the main parameter that any simulator should be able to predict.There are several different simulators used in industry for PLL simulations, eachone having its advantages and disadvantages. These include SPICE, EESof, Matlab, andanalytical/behavioral models. The main aspects that make a PLL difficult to simulate areas follows:• Two sources of feedback – main feedback (“loop” in phase-locked loop) andoscillator feedback [3]• High frequency clocks in conjunction with low frequency time constants[1][2]• Requires picosecond accuracy• Digital components mixed with analog components (mixed-mode)• Digital – phase detector, divider• Analog – voltage-controlled oscillator (VCO), charge pump, loop filterThe main aspects that may a simulator useful for modeling PLL’s are as follows:• Simulation speed• Modeling accuracy of CMOS processes• Accurate jitter prediction (clock stability)• Accurate lock-range prediction (frequency range over which the PLL willlock)3SPICESPICE is a well-known general-purpose time-domain circuit simulator [1][2].The concern when simulating PLL’s, is that there is a high frequency component such asthe clock that must be simulated in conjunction with low frequency components, such asthe lock time [1]. The clock period can be on the order of 1 ns and the time constantsassociated with the lock time (time required for PLL to phase/frequency lock on itsreference) can be in the milliseconds.To sample the 1 GHz square wave requires a sample roughly every 50ps for 1ms,it would require 20 million time points [2]. This is just for one node of the schematic.This in conjunction with doing a matrix solution for each time step for thousands oftransistors is not feasible in a reasonable amount of time.Although SPICE, given accurate models, can perform an accurate simulation, itcan be very time consuming. The utilization of a voltage-controlled tuned circuit as theVCO that does not require feedback to produce an oscillating output is a method that canbe used to reduce the simulation time [3], but still the number of data points andcalculations required is immense.The advantage of SPICE is that the models that accurately define a CMOSprocess are readily available. SPICE will typically always be used for determining theVCO frequency range and doing independent component tuning because of the superiormodel accuracy.MATLABMatlab is an analysis tool published by MathWorks. It has toolkits available foranalysis in areas such as DSP, communications, and control systems. Simulink is thegraphical interface for building simulation models.4Included with the communications toolkit are charge-pumped PLL models. Thesemodels run fairly fast but still generate large amounts of data. Another drawback ofMatlab is the included models would have to be significantly modified to simulate a PLLbuilt in a real CMOS process. Matlab still has the notion of time-steps which leads tosome of the same problems with SPICE, but doesn’t have to deal with transistor levelcalculations. Clearly accuracy would suffer if the analytical model didn’t mimic thebehavior in silicon.Efforts have been made to increase the accuracy of Matlab simulations by bettermodeling of the PLL blocks to reflect the CMOS process [4][5]. These effortsincorporate a CAD tool to create circuit prototypes of the functional block. Theprototypes mimic the behavior of the block and the input and output load characteristics.EESOFEESof is an extensive software tool published by HP. It has many differentmodules to it including microwave, RF, high speed interconnect, and device modelingand extraction.For PLL simulations, EESof uses a technique called circuit envelope simulation[2]. It accepts the input stimulus as RF carriers with time-varying complex envelopes(i.e. amplitude and phase modulations). The output solution is represented as a sum ofthe RF carriers and their harmonics, each with a time-varying complex envelope. CircuitEnvelope has a fundamental advantage over time-domain simulators in that the time step-size need only be small enough to capture the bandwidth of the modulation envelope(which is about 30kHz), instead of the RF carrier (which is 1 GHz) [1].The Circuit Envelope technique works well with the continuous time aspects ofthe PLL, but for components such as the digital phase detector would be more awkward.5PLL’s in communication applications use sinusoidal phase detectors which is more easilyused with EESof.ANALYTICAL/BEHAVIORAL MODELSTraditionally, the textbook s-domain PLL model has been used to model thebehavior of the loop in the locked state [9]. The input and output waveforms are assumedto be sinusoidal and the phase detector is modeled as a linear analog multiplier with aninherent ideal