EE100Su08 Lecture 9 July 16th 2008 Outline HW 1s and Midterm 1 returned today Midterm 1 notes HW 1 and Midterm 1 regrade deadline Wednesday July 23rd 2008 5 00 pm PST Procedure HW 1 Bart s office hours Midterm 1 Attach a note to the FRONT of your test with your complaint and drop it in HW box Questions This week Operational Amplifiers Op Amps Op Amp Model Negative Feedback for Stability Components around Op Amp define the Circuit Function Nonlinear circuits Op Amp from 2 Port Blocks EE100 Summer 2008 Slide 1 Bharathwaj Muthuswamy The Operational Amplifier The operational amplifier op amp is a basic building block used in analog circuits Its behavior is modeled using a dependent source When combined with resistors capacitors and inductors it can perform various useful functions amplification scaling of an input signal sign changing inversion of an input signal addition of multiple input signals subtraction of one input signal from another integration over time of an input signal differentiation with respect to time of an input signal analog filtering nonlinear functions like exponential log sqrt etc Isolate input from output allow cascading EE100 Summer 2008 Slide 2 Bharathwaj Muthuswamy Op Amp Terminals 3 signal terminals 2 inputs and 1 output IC op amps have 2 additional terminals for DC power supplies Common mode signal v1 v2 2 Differential signal v1 v2 V Inverting input v2 Non inverting input v1 positive power supply v0 output V negative power supply EE100 Summer 2008 Slide 3 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 4 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 5 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 6 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 7 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 8 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 9 Bharathwaj Muthuswamy Op Amp Notation and Model EE100 Summer 2008 Slide 10 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 11 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 12 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 13 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 14 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 15 Bharathwaj Muthuswamy Summing Point Constraint Check if under negative feedback Small vi result in large vo Output vo is connected to the inverting input to reduce vi Resulting in vi 0 Summing point constraint v1 v2 i1 i2 0 Virtual short circuit Not only voltage drop is 0 which is short circuit input current is 0 This is different from short circuit hence called virtual short circuit EE100 Summer 2008 Slide 16 Bharathwaj Muthuswamy Ideal Op Amp Analysis Technique Assumption 1 The potential between the op amp input terminals v v equals zero Assumption 2 The currents flowing into the op amp s two input terminals both equal zero No Potential Difference R2 R1 No Currents VIN V0 EXAMPLE EE100 Summer 2008 Slide 17 Bharathwaj Muthuswamy Ideal Op Analysis Non Inverting Amplifier Assumption 1 The potential between the op amp input terminals v v equals zero Assumption 2 The currents flowing into the op amp s two input terminals both equal zero KCL with currents in only two branches R1 R2 v v v in VIN R1 V0 vout EXAMPLE in out 0 R2 R1 R2 vin R1 Non inverting Amplifier VIN appears here EE100 Summer 2008 Slide 18 Bharathwaj Muthuswamy Non Inverting Amplifier Ideal voltage amplifier 2 v1 v2 vin i1 i2 0 v0 v2 vin vo Closed loop gain Av vin RL Use KCL At Node 2 R2 v0 v2 v2 0 i R2 R1 vo R1 R2 A vin R1 R1 vin Input impedance i EE100 Summer 2008 Slide 19 Bharathwaj Muthuswamy Ideal Op Amp Analysis Inverting Amplifier R2 R1 I2 VIN VR Voltage is VR RL V OUT VR VIN VR VOUT 0 R1 R2 Only two currents for KCL VOUT R2 Vin VR VR R1 Inverting Amplifier with reference voltage EE100 Summer 2008 Slide 20 Bharathwaj Muthuswamy Inverting Amplifier vo Closed loop gain Av vin Negative feedback checked Use summing point constraint R2 2 R1 v i 2 v0 vin v1 v1 v2 0 i1 i2 0 Use KCL At Node 2 vin v2 vout v2 i R1 R2 vo R2 vo R1 vin Input impedance R1 i RL Ideal voltage source independent of load resistor EE100 Summer 2008 Slide 21 Bharathwaj Muthuswamy Voltage Follower v0 v2 vin RL R2 0 R1 v0 v2 v2 0 i R2 R1 vo R1 R2 R2 A 1 1 vin R1 R1 EE100 Summer 2008 Slide 22 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 23 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 24 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 25 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 26 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 27 Bharathwaj Muthuswamy EE100 Summer 2008 Slide 28 Bharathwaj Muthuswamy Summing Amplifier v1 R1 R0 v2 R2 v3 EE100 Summer 2008 R3 v0 Slide 29 Bharathwaj Muthuswamy Difference Amplifier R2 v1 R1 v2 EE100 Summer 2008 v0 R3 R4 Slide 30 Bharathwaj Muthuswamy Integrator Want v K v dt o in What is the difference between R vin EE100 Summer 2008 V0 C Slide 31 Bharathwaj Muthuswamy Differentiator Want R C vin EE100 Summer 2008 Slide 32 v0 Bharathwaj Muthuswamy Nonlinear Opamp Circuits Start reading through online notes Introduction to nonlinear circuit analysis Outline Differences between positive and negative feedback Oscillator circuit EE100 Summer 2008 Slide 33 Bharathwaj Muthuswamy High Quality Dependent Source In an Amplifier AMPLIFIER SYMBOL Differential Amplifier V V A AMPLIFIER MODEL V0 A V V Circuit Model in linear region V0 Ri V1 AV1 V0 depends only on input V V See the utility of this this Model when used correctly mimics the behavior of an amplifier but omits the complication of the many many transistors and other components EE100 Summer 2008 Slide 34 Bharathwaj Muthuswamy V0 Model for Internal Operation A is differential gain or open loop gain Ideal op amp A Ri Ro 0 Circuit Model v1 i1 Ro io Ri Common mode gain 0 vcm v1 v2 2 vd v1 v2 v2 vo Acm vcm Ad vd i2 vo A v1 v2 Since vo A v1 v2 Acm 0 EE100 Summer 2008 Slide 35 Bharathwaj Muthuswamy Model and Feedback Negative feedback Circuit Model connecting the output port to the negative input port 2 Positive feedback connecting the output port to the positive input port 1 Input impedance R looking into the input terminals Output impedance Impedance in series with the output terminals EE100 Summer 2008 v1 i1 Ro io Ri v2 Slide 36 i2 vo A v1 v2 Bharathwaj Muthuswamy Op Amp and Use of Feedback A very high gain differential amplifier can function in an extremely linear fashion as an operational amplifier by using negative feedback R1 VIN R1 R2 V0 R2 Ri VIN
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