Nanotechnology Addendum Nanowire Integration Techniques for Massively Parallel Manufacturable Electronic Photonic Devices M Saif Islam ECE Department UC Davis saif ucdavis edu S Sharma T I Kamins R Stanley Williams HP Laboratories Palo Alto CA 94304 Device size and density Physically small features Operation with small features Limited number of electrons Interconnections Electrons per Device CMOS Scaling Critical Issues Moore s Law Number of Electrons 10 4 3 10 2 10 10 Analog Digital Basic device physics 1 0 1 1988 1996 2004 2012 2020 Year IC Fabrication Facility Cost B Moore s Second Law Cost Minimize expensive lithography Cost of IC Fabrication Facility 100 Self or directed assembly Simpler architecture 10 Defect tolerant architecture 1 1995 2000 2005 Year 2010 Will Device Size Keep Shrinking Carbon nanotubes Transistor Size nm 10000 Optical Lithography 1000 DNA Extreme UV 100 10 DNA 1 1980 2000 2020 Year 2040 Nanowires ENIAC circa 1947 15 000 vacuum tubes and weighs 30 tons ENIAC circa 1947 108 Shrink volume by Improve power efficiency by 108 iPAQ 2002 Synthesis of Nanowires Sunkara Some et al Examples Lieber et al Wang et al Fukui et al Yang et al 2 m Islam et al Xia et al Busbee et al Kamins et al Cao et al Samuelson et al Meyyappan et al Gundiah et al Ag Au Zn InP ZnO Si Ge Si Ge SiGeC GaAs ZnS GaN InGaAs In2O3 and other materials Applications of Nanowires MOS Transistor Interconnect NW Gate Dielectric Crossed NW FET decoders Chemical Sensor Transistor laser LED Electron emitter AFM or STM probes Interconnect for molecular electronics decoders Optical Sensor Electrical sensor Photonic crystals test bed for SERS for single molecule sensing Biological Sensor
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