Week 14a Propagation delay of logic gates CMOS complementary MOS logic gates Pull down and pull up The basic CMOS inverter Current flow and power dissipation in CMOS circuits Equation for power dissipated in N logic circuits clocked at frequency f EE42 100 Spring 2006 Week 14a Prof White 1 WHAT IS THE ORIGIN OF GATE DELAY Logic gates are electronic circuits that process electrical signals Most common signal for logic variable voltage Specific voltage ranges correspond to 0 or 1 Volts 3 2 1 0 Range 1 Thus delay in voltage rise or fall because of delay in charging internal capacitances will translate to a delay in signal timing Gray area not allowed Range 0 Note that the specific voltage range for 0 or 1 depends on logic family and in general decreases with succeeding logic generations EE42 100 Spring 2006 Week 14a Prof White 2 INVERTER VOLTAGE WAVEFORMS TIME FUNCTIONS Inverter input is v t output is v t IN OUT Inverter inside a large system v IN t v OUT t Vin t t EE42 100 Spring 2006 Week 14a Prof White 3 GATE DELAY PROPAGATION DELAY Define as the delay required for the output voltage to reach 50 of its final value In this example we will use 3V logic so halfway point is 1 5V Inverters are designed so that the gate delay is symmetrical rise and fall Vin t 1 5 t Vout t Approximation 1 5 EE42 100 Spring 2006 D Week DWhite D 14a Prof t 4 EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEED Computer architects would like each system clock cycle to have between 20 and 50 gate delays use 35 for calculations Implication if clock frequency 500 MHz clock period 5 108 s 1 1 Period 2 10 9s 2 ns nanoseconds Gate delay must be D 1 35 Period 2 ns 35 57 ps picoseconds How fast is this Speed of light c 3 108 m s Distance traveled in 57 ps is c X D 3x108m s 57x10 12s 17 x 10 4 m 1 7cm EE42 100 Spring 2006 Week 14a Prof White 5 WHAT DETERMINES GATE DELAY v OUT t v IN t The delay is mostly simply the charging of the capacitors at internal nodes Logic gates consist of just CMOS transistor circuits CMOS complementary metal oxide semiconductor NMOS and PMOS FETs together Let s recall the FET EE42 100 Spring 2006 Week 14a Prof White 6 Modern Field Effect Transistor FET An electric field is applied normal to the surface of the semiconductor by applying a voltage to an overlying gate electrode to modulate the conductance of the semiconductor Modulate drift current flowing between 2 contacts source and drain by varying the voltage on the gate electrode N channel metal oxidesemiconductor field effect transistor NMOSFET EE42 100 Spring 2006 Week 14a Prof White 7 Pull Down and Pull Up Devices In CMOS logic gates NMOSFETs are used to connect the output to GND whereas PMOSFETs are used to connect the output to VDD An NMOSFET functions as a pull down device when it is turned on gate voltage VDD A PMOSFET functions as a pull up device when it is turned on gate voltage GND VDD Pull up network PMOSFETs only F A1 A2 AN EE42 100 Spring 2006 A1 A2 AN input signals A1 A2 AN Pull down network Week 14a Prof White NMOSFETs only 8 Controlled Switch Model G Input RN Output S G Input RP Output Type N controlled switch means switch is closed if input is high VG VS Type P controlled switch means switch is closed if input is low VG VS S Now lets combine these switches to make an inverter EE42 100 Spring 2006 Week 14a Prof White 9 The CMOS Inverter Current Flow during Switching N sat P sat VOUT VDD N off P lin VDD S G i VOUT A D G C N sat P lin D VIN i B E N lin P sat S N lin P off 0 0 EE42 100 Spring 2006 D Week 14a Prof White VDD VIN 10 CMOS Inverter Power Dissipation due to DirectPath Current VDD VDD VDD VT vIN S G D i vIN 0 Ipeak vOUT D G S VT i 0 tsc time Note once the CMOS circuit reaches a steady state there s no more current flow and hence no more power dissipation Energy consumed per switching period EE42 100 Spring 2006 Week 14a Prof White Edp t scVDD I peak 11 Controlled Switch Model of Inverter VDD 2V SP is closed if VIN VDD SP RP VIN VOUT RN Input SN SN is closed if Output VIN VSS VSS 0V So if VIN is 2V then SN is closed and SP is open Hence VOUT is zero But if VIN is 0V then SP is closed and SN is open Hence VOUT is 2V EE42 100 Spring 2006 Week 14a Prof White 12 Controlled Switch Model of Inverter VDD 2V VIN 2V RN V SS 0V VOUT IF VIN is 2V then SN is closed and SP is open Hence VOUT is zero but driven through resistance RN VDD 2V RP VIN 0V VOUT 0V VSS EE42 100 Spring 2006 But if VIN is 0V then SP is closed and SN is open Hence VOUT is 2V but driven through resistance RP Week 14a Prof White 13 Controlled Switch Model of Inverter load capacitor charging and discharging takes time VDD 2V VIN 2V RN V SS 0V VOUT IF there is a capacitance at the output node there always is then VOUT responds to a change in VIN with our usual exponential form VOUT VDD 2V VIN jumps from 2V to 0V RP VIN 0V VOUT 0V VSS EE42 100 Spring 2006 Week 14a Prof White VIN jumps from 0V to 2V t 14 Calculating the Propagation Delay Model the MOSFET in the ON state as a resistive switch Case 1 Vout changing from High to Low input signal changed from Low to High NMOSFET s connect Vout to GND VDD tpHL 0 69 RnCL Pull up network is modeled as an open switch vIN VDD Pull down network is modeled as a resistor EE42 100 Spring 2006 Week 14a Prof White Rn CL vOUT 15 Calculating the Propagation Delay cont d Case 2 Vout changing from Low to High input signal changed from High to Low PMOSFET s connect Vout to VDD VDD tpLH 0 69 RpCL Pull up network is modeled as a resistor Rp vIN 0 V Pull down network is modeled as an open switch EE42 100 Spring 2006 Week 14a Prof White CL vOUT 16 Output Capacitance of a Logic Gate The output capacitance of a logic gate is comprised of several components pn junction and gate drain capacitance both NMOS and PMOS transistors capacitance of connecting wires extrinsic capacitance input capacitances of the fan out gates intrinsic capacitance EE42 100 Spring 2006 Week 14a Prof White 17 Reminder Fan Out Typically the output of a logic gate is connected to the input s of one or more logic gates The fan out is the number of …
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