DATA SHEETProduct specificationFile under Integrated Circuits, IC02January 1990INTEGRATED CIRCUITSSAA1101Universal sync generator (USG)January 1990 2Philips Semiconductors Product specificationUniversal sync generator (USG) SAA1101FEATURES• Programmable to seven standards• Additional outputs to simplify signal processing• Can be synchronized to an external sync. signal• Option to select the 524/624 line mode instead of the 525/625 line mode• Lock from subcarrier to line frequencyGENERAL DESCRIPTIONThe SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras,film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043sync generator and the SAA1044 subcarrier coupling IC.QUICK REFERENCE DATAORDERING AND PACKAGE INFORMATIONNotes1. SOT117-1; 1996 December 02.2. SOT136-1; 1996 December 02.SYMBOL PARAMETER MIN. MAX. UNITVDDsupply voltage range (pin 28) 4.5 5.5 VIDDquiescent supply current − 10 µAfOSCclock oscillator frequency − 24 MHzEXTENDEDTYPE NUMBERPACKAGEPINS PIN POSITION MATERIAL CODESAA1101P 28 DIL plastic SOT117(1)SAA1101T 28 SO28 plastic SOT136A(2)January 1990 3Philips Semiconductors Product specificationUniversal sync generator (USG) SAA1101k, full pagewidthMGH191COMBININGLOGICVERTICALDIVIDERRESETPULSESHAPERADDITION/SUPPRESSIONLOGICSTANDARDPROGRAMMEDDIVIDERLINEDIVIDERHORIZONTALDETECTIONVERTICALDETECTIONVERTICALLOCKSUBCARRIERDIVIDERSUBCARRIERSUBTRACTIONLOCK MODESELECTIONPHASEDETECTION1817161522212019CSCBBKIDHDVDWMPCLP12RR7VLE11ECSfs − ∆ffs∆ffHHref40fHHRIfH2fH160fHPRESCALERSAA110181428 910PH LM1 LM0NORM SI13232434CS1 CLOCS0VSSVDDXYZFSOFSIOSCOOSCI2526272165Fig.1 Block diagram.January 1990 4Philips Semiconductors Product specificationUniversal sync generator (USG) SAA1101FUNCTIONAL DESCRIPTIONGeneration of pulsesGeneration of standard pulses suchas sync, blanking and burst for TVsystems: PAL B/G, PALN, PALM,SECAM and NTSC. In addition anumber of non-standard pulses havebeen supplied to simplify signalprocessing. These signals include -horizontal drive, vertical drive, clamppulse, identification etc. It is possibleto select the 524/624 line modeinstead of the 525/625 line mode forall the above TV systems forapplications such as robotics, gamesand computers.Fig.2 Pinning configuration;SOT117.fpageFSIFSOCS1CS0OSCIOSCOVLEPHLM1LM0ECSRRSIVSSVDDZYXNORMHDCLOVDWMPCLPCSCBBKID12345678910111213282726252423222120191817161514SAA1101MGH190PINNINGSYMBOL PIN DESCRIPTIONFSI 1 subcarrier oscillator input, where fmax = 5 MHzFSO 2 subcarrier oscillator outputCS1 3 clock frequency selection - CMOS inputCS0 4 clock frequency selection - CMOS inputOSCI 5 clock oscillator input, where fmax = 24 MHzOSCO 6 clock oscillator outputVLE 7 vertical in-lock enable - CMOS inputPH 8 phase detector output - 3-state outputLM1 9 lock mode selection - CMOS inputLM0 10 lock mode selection - CMOS inputECS 11 external composite sync. signal - CMOS Schmitt-triggerinputRR 12 frame reset - CMOS Schmitt-trigger inputSI 13 set identification, used to set the correct field sequence inPAL-mode. The correction (inversion of fH2) is done at theleft-hand slope of the SI-pulse. Minimum pulse width is800 ns. CMOS Schmitt-trigger input.VSS14 groundID 15 identification - push-pull outputBK 16 burst key (PAL/NTSC), chroma-blanking (SECAM) -push-pull outputCB 17 composite blanking - push-pull outputCS 18 composite sync. - push-pull outputCLP 19 clamp pulse - push-pull outputWMP 20 white measurement pulse-3-state outputVD 21 vertical drive pulse - push-pull outputHD 22 horizontal drive pulse - push-pull outputNORM 23 used with X, Y and Z to select TV system; NORM = 0,625/525 line mode (standard);NORM = 1, 624/524 line mode - CMOS inputCLO 24 clock output - push-pull outputX 25 TV system selection input - CMOS inputY 26 TV system selection input - CMOS inputZ 27 TV system selection input - CMOS inputVDD28 voltage supplyJanuary 1990 5Philips Semiconductors Product specificationUniversal sync generator (USG) SAA1101Lock modesThe USG offers four lock modes:• Lock from the subcarrier• Slow sync. lock, external Href• Slow sync. lock, internal Href• Fast sync. lock, internal HrefLOCK FROM SUBCARRIERLock from subcarrier to the line frequency for the abovementioned TV systems is given below; the horizontalfrequency (fH) = 15.625 kHz for 625 line systems and15.734264 kHz for 525 line systems.These relationships are obtained by the use of a phaselocked loop and the internal programmed divider chain,see Fig.3(a).LOCK TO AN EXTERNAL SIGNAL SOURCEThe following methods can be used to lock to an externalsignal source:1. Sync. lock slow; the line frequency is locked to anexternal signal. The line and frame information areextracted from the external sync. signal and usedseparately in the lock system. The line information isused in a phase-locked loop where external andinternal line frequencies are compared by the samephase detector as is used for the subcarrier lock. Theexternal frame information is compared with theinternal frame in a slow lock system; mismatch ofinternal and external frames will result in the additionor suppression of one line depending on the directionof the fault. The maximum lock time for frame lock is6.25 s, see Fig.3(b).2. Sync. lock fast. A fast lock of frames is possible with aframe reset which is extracted out of the incomingexternal sync. signal, see Fig.3(c).3. Sync. lock with external reference. Lock of an externalsync. signal to the line frequency with an external linereference to make possible a shifted lock. TheSECAM (1 and 2) 282fHPALN 229.2516fHNTSC (1 and 2) 227.5fHPALM 227.25fHPAL B/G 283.7516fHsubcarrier input is, in this case, used as an externalinput for the horizontal reference, see Fig.3(d).SELECTION OF LOCK MODELock mode is selected using the inputs LM0 and LM1 asillustrated in the Table below.LM0 LM1 SELECTION0 0 lock to subcarrier0 1 slow sync. lock external Href1 0 slow sync. lock internal Href1 1 fast sync. lock internal HrefJanuary 1990 6Philips Semiconductors Product specificationUniversal sync generator (USG) SAA1101The different lock modes are illustrated by the following figures:Fig.3 (a) Lock to subcarrier.Fig.3 (b) Slow sync lock, internal HrefFig.3 (c) Fast sync lock, internal HrefFig.3 (d) Slow sync lock, external Hrefhandbook, halfpageMGH193n × fHLINEOSCILLATOR FSOFSIOSCO OSCISAA1101SUB-CARRIEROSCILLATORPHLM1LM0logic 0 logic 110658219handbook,