Instruction Set6-1Instruction Set Nomenclature:Status Register (SREG):SREG: Status registerC: Carry flag in status registerZ: Zero flag in status registerN: Negative flag in status registerV: Twos complement overflow indicatorS: N ⊕ V, For signed testsH: Half Carry flag in the status registerT: Transfer bit used by BLD and BST instructionsI: Global interrupt enable/disable flagRegisters and operands:Rd: Destination (and source) register in the register fileRr: Source register in the register fileR: Result after instruction is executed K: Constant literal or byte data (8 bit)k: Constant address data for program counterb: Bit in the register file or I/O register (3 bit)s: Bit in the status register (3 bit)X,Y,Z: Indirect address register (X=R27:R26,Y=R29:R28 and Z=R31:R30)P: I/O port addressq: Displacement for direct addressing (6 bit)I/O RegistersRAMPX, RAMPY, RAMPZ: Registers concatenated withthe X, Y and Z registers enabling indirect addressing of thewhole SRAM area on MCUs with more than 64K bytesSRAM.Stack:STACK:Stack for return address and pushed registersSP: Stack Pointer to STACKFlags:⇔: Flag affected by instruction0: Flag cleared by instruction1: Flag set by instruction-: Flag not affected by instructionConditional Branch Summary* Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr → CP Rr,RdTest Boolean Mnemonic Complementary Boolean Mnemonic CommentRd > Rr Z•(N ⊕ V) = 0 BRLT* Rd ≤ Rr Z+(N ⊕ V) = 1 BRGE* SignedRd ≥ Rr (N ⊕ V) = 0 BRGE Rd < Rr (N ⊕ V) = 1 BRLT SignedRd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE SignedRd ≤ Rr Z+(N ⊕ V) = 1 BRGE* Rd > Rr Z•(N ⊕ V) = 0 BRLT* SignedRd < Rr (N ⊕ V) = 1 BRLT Rd ≥ Rr (N ⊕ V) = 0 BRGE SignedRd > Rr C + Z = 0 BRLO* Rd ≤ Rr C + Z = 1 BRSH* UnsignedRd ≥ Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS UnsignedRd = Rr Z = 1 BREQ Rd ≠ Rr Z = 0 BRNE UnsignedRd ≤ Rr C + Z = 1 BRSH* Rd > Rr C + Z = 0 BRLO* UnsignedRd < Rr C = 1 BRLO/BRCS Rd ≥ Rr C = 0 BRSH/BRCC UnsignedCarry C = 1 BRCS No carry C = 0 BRCC SimpleNegative N = 1 BRMI Positive N = 0 BRPL SimpleOverflow V = 1 BRVS No overflow V = 0 BRVC SimpleZero Z = 1 BREQ Not zero Z = 0 BRNE SimpleInstruction Set6-2Complete Instruction Set Summary√ ) Not available in base-line microcontrollers(continued)Mnemonics Operands Description Operation Flags #ClockNoteARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rd, K Add Immediate to Word Rd+1:Rd ← Rd+1:Rd + K Z,C,N,V 2SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rd, K Subtract Immediate from Word Rd+1:Rd ← Rd+1:Rd - K Z,C,N,V 2AND Rd, Rr Logical AND Rd ← Rd . Rr Z,N,V 1ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V 1OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V 1INC Rd Increment Rd ← Rd + 1 Z,N,V 1DEC Rd Decrement Rd ← Rd - 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← $FF None 1CP Rd,Rr Compare Rd - Rr Z,C,N,V,H, 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,H 1CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,H 1Instruction Set6-3Complete Instruction Set Summary (continued)(continued)Mnemonics Operands Description Operation Flags #ClockNoteBRANCH INSTRUCTIONSRJMP k Relative Jump PC ← PC + k + 1 None 2IJMP Indirect Jump to (Z) PC ← Z None 2JMP k Jump PC ← k None 3RCALL k Relative Call Subroutine PC ← PC + k + 1 None 3ICALL Indirect Call to (Z) PC ← Z None 3CALL k Call Subroutine PC ← k None 4RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACK I 4CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3SBRC Rr, b Skip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None 1 / 2 / 3SBRS Rr, b Skip if Bit in Register Setif (Rr(b)=1) PC ← PC + 2 or 3None 1 / 2 / 3SBIC P, b Skip if Bit in I/O Register Clearedif(I/O(P,b)=0) PC ← PC + 2 or 3None 1 / 2 / 3SBIS P, b Skip if Bit in I/O Register SetIf(I/O(P,b)=1) PC← PC + 2 or 3None 1 / 2 / 3BRBS s, k Branch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None 1 / 2BRBC s, k Branch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None 1 / 2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1 / 2BRNE k Branch if Not Equalif (Z = 0) then PC ← PC + k + 1None 1 / 2BRCS k Branch if Carry Setif (C = 1) then PC ← PC + k + 1None 1 / 2BRCC k Branch if Carry Clearedif (C = 0) then PC ← PC + k + 1None 1 / 2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1 / 2BRLO k Branch if Lowerif (C = 1) then PC ← PC + k + 1None 1 / 2BRMI k Branch if Minusif (N = 1) then PC ← PC + k + 1None 1 / 2BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1None 1 / 2BRGE k Branch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC+ k + 1None 1 / 2BRLT k Branch if Less Than, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None 1 / 2BRHS k Branch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None 1 / 2BRHC k Branch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None 1 / 2BRTS k Branch if T Flag Setif (T = 1) then PC ← PC + k + 1None 1 / 2BRTC k Branch if T Flag Clearedif (T = 0) then PC ← PC + k …