Bipolar Transistor Operating Modes Active Mode Vce 0 3V Vbe 0 7V Cuto Mode Ice 0 Vbe 0 7V Saturation Vce 0 3V Vbe 0 7V Reverse Mode Vbe 0 7V Vbc 0 7V BJT Flow Chart CMOS NAND Gate Vdd AB B A CMOS NOR Gate Q4 Q3 F A Q1 Q2 B CMOS Transmission Gate Power Active Power Re VRM S IRM S Reactive Power Im VRM S IRM S Apparent Power jVRM S IRM S j Total Power in Balanced 3 3 P Power Factor Active Power Apparent Power Power Factor cos Power Factor Correction Eliminate Reactive Power Always Uses Reactive Element IP F C jIm IL XP F C 1 Im 1 ZL Synchronous Machine Phasor Diagram Induction Motor Model R0 jX 0 N1 N2 R00 N1 N2 2 R2 R0 R1 R00 X 0 X1 N1 N2 2 X2 1 s 2 s R2 Mechanical Power per Phase 00 2 s 1 s R V 0 P sR0 1 s R00 2 s2 X 02 Conjugate Match Maximizes Power XL opt XT RL opt RT ZL opt ZT jVT j2 Pmax 8RT Parallel L C Circuit I R I C Vout L Vout R j L IZ I 1 2 LC j RC Parallel L C Circuit II I R Vout I Z I L C Vout j L 1 2 LC j L R 1 LC Q R 0 L 2 0 General DC Circuit Example X A 8V 8 24 Y 4 1A B 1 1A 2V KCL equations Kircho s Current Law KCL at Node X VY V X 1 0 8 24 4 KCL at Node Y VX V Y 2 VY 1 0 1 4 8 VX VX KCL equations Contd Collecting terms 10 1 VX VY 2 24 4 1 5 VX VY 1 4 4 KCL equations Contd Rationalized Matrix Equation 0 B B B B 1 0 1 0 1 B 24 C 5 3 CCC BBB VX CCC B C B C C B C B C A A A VY 1 5 4 KCL equations Contd Solve by Cramer s Rule 25 30 22 1 B 24 3 C B C 1 B C C 6 VX det B A 4 5 0 1 B C 5 24 B C 1 B C C 2 VY det B A 1 4 Transformations Box A 8 8V 1A 1A 8 24 1A 8 2A 6 Thevenin Equiv Box A 6 2A 6 12V Transformations Box B 1 2V 2A 1 1A 2A 1 1A 1 Thevenin Equiv Box B 1 1A 1 1V Solution w Thevenin Equivs 6 12V X 4 Y 1 1A VX 12 6 1 6 VY 1 1 1 2 1V
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