EE290C – Spring 2011Lecture 4: Timing BasicsElad AlonDept. of EECSEE290C Lecture 4 2Why We Need to Talk About TimingEE290C Lecture 4 3Clocking Types• Many different options…• All boil down to relationship between (or even existence of) clk1and clk2EE290C Lecture 4 4Clocking Types*Poulton’99EE290C Lecture 4 5“Simple” Synchronous System• Under what conditions will this work?• “EE141” answer:EE290C Lecture 4 6What You Really DoEE290C Lecture 4 7An Example• tp,data= 2ns, Tbit= ?• What else do you need to know?EE290C Lecture 4 8An Example• tp,data= 2ns, Tbit= ?EE290C Lecture 4 9An Example• tp,data= 2ns, tsk+jitt= +/-50ps• Get “bands” of functionality:100 150 200 250 300 3506789101112131415Tbit (ps)# of bits on the lineEE290C Lecture 4 10Source Synchronous Clocking• Key idea: match clock and data paths• Link ideally works from DC up to timing uncertainty-limited frequency• What is the “right” tdel?EE290C Lecture 4 11Source Synchronous Clocking• Want one clock “link” for multiple data links• Reduce overhead• What if data lines don’t match each other?• Or don’t match clock line• Or tdelisn’t quite right (depends on Tbit, PVT, etc.)EE290C Lecture 4 12Realistic Source Synchronous SystemclkDQD0tp,data,0tp,data,cDQD1tp,data,1TXTXTXDRX0tdel0RXRXDRX1tdel1DQDQRXEE290C Lecture 4 13In General: CDR• CDR = Clock and Data Recovery• Recover clock phase and/or frequency based on data itself• If phase only, need a frequency reference• Several advantages vs. fixed timing• Don’t have to match delays/paths (mesochronous)• Allows separate crystals (plesiochronous)• But, CDR isn’t free• And places some requirements on dataEE290C Lecture 4 14Conceptual CDREE290C Lecture 4 15Linear (Hogge) Phase DetectorEE290C Lecture 4 16Bang-Bang (Alexander) Phase Detector• Edge clock Tsym/2 away from data• Derive early/late from data and edge samples:• Dn: (dn!= en) & (dn-1!= dn) • Up: (dn== en) & (dn-1!= dn)edge Clkdata ClkdnenVinEE290C Lecture 4 17Phase Adjustment• Many possibilities…• DLL vs. PLL• VCO vs. VCDL• Digital vs. analog• Etc.• All boil down to adjusting delay, frequency, or both• More in a few weeksEE290C Lecture 4 18CDR in Plesiochronous System• Transmit data @ f1• Recover clock and data @ f1 on RX• Elastic buffer (FIFO) transfers data from f1 to f2PLL CDRSerializerFIFODeserializerTx RxElasticBuffer10 bits@ f110 bits@ f110 bits@ f2f2f1CHIP 1CHIP 2LogicLogicfrom other linksEE290C Lecture 4 19Implications• FIFO must be deep enough• Set by max. freq. offset, data length• CDR must be able to track max. freq. offsetPLL CDRSerializerFIFODeserializerTx RxElasticBuffer10 bits@ f110 bits@ f110 bits@ f2f2f1CHIP 1CHIP 2LogicLogicfrom other linksEE290C Lecture 4 20Final Notes: Parallel vs. Serial LinksEE290C Lecture 4 21Final Notes: Clock