Digital Controller for an Interleaved Voltage RegulatorSeth R. SandersAngel V. PeterchevJinwen [email protected]@[email protected] DepartmentU.C. BerkeleyBerkeley, CA 94720DIGITAL PWM CONTROL—Motivation• Develop Low-Cost High-Flexibility Digital Controllers for broad range of PWM Control Applications (e.g. high quality power supply for next generation of Pentium CPU’s for desktop and portable computing)• Capture high frequency applications (>500 KHz) not usually addressed with existing digital controllersWhy Digital• Matching duty cycles among all phases in multi-phase converter, thus eliminating the need of current sensing at each phase• Immune to analog component variations on chip• Implement sophisticated control schemes for better performance• Programmable by a digital system like the CPU• Technology Scaling, shorter design periodIssues• Controller Architecture • Resolution—A/D, D/A• Development of control schemes that account for the non-linearity inherent in a quantizedsystem• IC implementation of cost- and power-efficient modules such as PWM generation and A/D, D/A conversion functionsApplication: 4-Phase Buck VRMDAC levelsADC levels0 bit error bin-1 bit error bin1 bit error bintransientsteady stateVoutSystem Issues:Steady state limit cycling of Voutresulting from quantization♦ Problem:Limit Cycling—Steady-state oscillations of Voutdue to thequantization in the feedback loop. ♦ Solution:— To ensure that there is a steady-state DAC (DPWM) level in the zero-error bin,resolution (DAC) > resolution (ADC) (a factor of 2 seems sufficient)—Slow Integrator to settle Voutto the zero-error bin of the ADCADC and DAC Resolution RequirementsDAC levelsADC levels0 bit error bin-1 bit error bin1 bit error bintransientsteady stateVoutTransient response with res(DAC) = 2 • res(ADC) , and an integrator1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.51.911.921.931.941.951.961.971.981.9922.01 Vout time (msec) light load ← → heavy load ADC levels ↓ ↑reference voltage bin ↓ Limit cycling ↑in steady stateTransient Response without Integrator (simulation)Vin = 5 V , Vref = 2 V, res (ADC) = 8 bit , res (DAC) = 9 bit1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.51.911.921.931.941.951.961.971.981.9922.01 Vout time (msec) light load ← → heavy load ADC levels ↓ ↑reference voltage bin ↓ ↑No limit cyclingin steady stateTransient Response with Integrator (simulation)Vin = 5 V , Vref = 2 V, res (ADC) = 8 bit , res (DAC) = 9 bit♦ Problem:To provide accurate positioning of the output voltage at the order of 5 mV, the resolution of the DAC (DPWM) has to be 10 bit with 5 V input. This resolution requires a DPWM module witha large number of stages running at a high frequency → high power dissipation.♦ Solution:Sub-Bit Positioning—use a DPWM module with lower hardware resolution (e.g. 7 or 8 bits) and add digital dither to the duty cycle to produce finer (sub-bit) levels of Vout. Introducing Sub-Bit Positioningm-bitcounterfswswitching frequencym x mlook-uptableDcduty cyclem n + msaturatedn-bit addernDc’ditheredduty cycle1 (LSB)n (MSB’s)m (LSB’s)Structure for Adding Arbitrary Dither Patterns to the Duty CycleSawtooth dither pattern00 01 10 1100011011Tsw* 4Tsw* 4♦ Modified dither patterns have higher frequency for some sub-bit levels, and hence produce smaller ripple on Vout Modified dither pattern00 01 10 11DcLSB’scounter0¼½¾Averaged sub-bit levelsDither Patterns Added To The Duty Cyclevs. Counter (Example For m = 2 Bits)1.5 2 2.5 3 3.5 4 4.5 5 5.5 61.921.931.941.951.961.971.981.9922.01 Vout time (msec)Transient Response with Sub-Bit Positioning 11-bit ADC , 9-bit DAC + 3-bit SBP = effectve 12-bit DAC → heavy load↓↑reference voltage binVout finds a steady state within the reference bin due to the effective increase in DAC resolutionTransient Response with Sub-Bit Positioning= effectiveVoutIominIomaxIout∆Io*ResrLoad StepUsual converter responseResponse with optimal voltage positioning2 * ∆Io *ResrVoutOptimal Voltage PositioningWhat is it?∆IoRe*mVcCo/m_+ReCoKeVrefVinL1VoutReVo’ = Vout + Re * IoutdigitalcontrollerILIoutIcRe * Iout = Re * (IL+ Ic) = Re * IL+ (Vc – Vout)Advantage: Doesn’t add a resistive current sensor for Iout after Co (the voltage drop across such sensor would add to the ESR drop during transients).Ic estimatorerror amplifierImplementation of Optimal Voltage Positioningwith ILand ICsensing---Vo’ = Vc + Re * IL1 2 3 4 5 61.91.921.941.961.9822.02 volts time (msec) → max load Vout ↓ ↑reference bin ↓ ↑Vout + Iout• ResrTransient Response with Voltage Positioning (simulation)Vin = 5 V , Vref = 2 V, res (ADC) = 8 bit , res (DAC) = 9 bitPro’s:♦ Resr can be increased by a factor of 2Output capacitor size can be reduced by a factor of 2.♦ Simple 3-level ADC (e.g. two comparators) can be used, since the controlled quantity Vo’ has small excursions from the reference bin.Con’s:♦ Output current sensing required.♦ Value of Resr should be known.Pro’s and Con’s of Voltage Positioning5 bit VID from microprocessorVeVrefVoutRe*mVcCo/mReCoVinL1ReVo’ = Vout + Re * Iout_+Kesimple3,5-levelADC5,6bitslowDACPIDSBPDPWMfeedforwardto other phasesdigital moduleerror amplifierIL= Σ ILiall phases♦This architecture avoids individual sensing of the different phase currentsBlock Diagram of Proposed Controller Architecturewith ILsensing and ICestimation---550 600 650 700 750 800 850 900 950 10001.91.921.941.961.9822.022.04 Vout (V) time (usec)Step Response with Voltage Positioning and Sub-Bit Positioning(simulation) Vin= 5V, Vref= 2V, Resr= 3.5mΩ, ∆I = 10A,res(9-Bit ADC) = 10mV, res(DAC) = 5mV (7 bit + 3 bit dither = 10 bit)Transient before the integrator has adjustedESR dropsteady-state (no limit cycling)Load step∆I = 10AStep Response with Voltage Positioning and Sub-Bit Positioning(test waveform) Vin= 5V, Vref= 2V, Resr= 3.5mΩ, ∆I = 10A,res(9-Bit ADC) = 10mV, res(DAC) = 5mV (7 bit + 3 bit dither = 10 bit)transient before the integrator has adjustedESR dropsteady-state (no limit cycling)Load step∆I = 10APWM Generation Scheme—A Ring-Mux StructureRing Oscillator and Multiplexer DetailTest Waveform (1)Differential outputs in one of 128 stages(1MHz)Test Waveform (2)4ns Outputs of 2 adjacent stages, showing 1 LSB phase shiftOscillation Freq. = 1MHz, 1LSB = 1µs • 1/28= 4nsPWM Generation Scheme 2—Counter-Comparator