EE290C – Spring 2011Lecture 3: Basic Transmitters and ReceiversElad AlonDept. of EECSEE290C Lecture 3 2• Elad will be out of town this Thurs.• Make-up lecture will be held on Mon. 1-31 1:30-3:00pm in 127 Dwinelle• Office hours on Thurs. cancelled – available over emailAdministrativeEE290C Lecture 3 3Plain Old Inverters – Why Not?EE290C Lecture 3 4• Signaling Basics• Single-ended vs. differential• “Current-mode” vs. “Voltage-mode” signaling• Termination• TX Circuit Design• Z control• CML, VM drivers• Power vs. swing• Serialization optionsOutline• RX Circuit Design • Comparator review• DeserializationoptionsEE290C Lecture 3 5• RX: comparing against a shared reference• Reference may be implicit (i.e., ground/supply)• Mismatch between shared and individual lines• TX: generates large variations on power supply• SSO – simultaneous switching outputs• No XTALK immunitySingle-Ended SignalingdinCdCrrefrcvrdoutxmtrEE290C Lecture 3 6So Why Even Mention This?EE290C Lecture 3 7Classic Debate• “Differential must be twice as fast as single-ended in order to win”• Reality more complicated• E.g., power supply to signaling pin ratio higher in S.E.• Short “answer”• Differential a lot easier to build and get right the first time• Can make S.E. work – but often a lot more painfulEE290C Lecture 3 8“Voltage-Mode” vs. ”Current-Mode”• Transmission line has both voltage and current…• Terminology unfortunately heavily overloaded• Whether or not Zo of driver is high• How Zo of driver is set• What sets output swingEE290C Lecture 3 9“Voltage-Mode” vs. ”Current-Mode”EE290C Lecture 3 10Another View+-+-VSVS/2shared+-refd+-dd“High Impedance”DifferentialSingleEnded“Low Impedance”• RX opposite of TX• Signal integrity implications?EE290C Lecture 3 11Why Terminate?EE290C Lecture 3 12External vs. Internal Termination• Internal: makes package L, pad C part of T-line• External: chip/package become a stub• If want on-die term need to control its value…EE290C Lecture 3 13Untrimmed Poly Termination• Main issue is variation: +/-20% at one temperature• But• It’s relatively linear • ESD robust• Low parasitics…EE290C Lecture 3 14Ri, Ci, and Pad Complexity• LPF at pad can dominate overall channel• Example: 500fF ESD, 500fF driver, 500fF wire• Bandwidth ~4GHz with double-terminated link• Even worse in busses (or if add big series R)…LICIRsLCGdRI0.000.200.400.600.801.001e+008 1e+009Normalized amplitude Freq (Hz)"low_CL""1_drop""2_drop""4_drop""8_drop"Ci, Ritypically dominateEE290C Lecture 3 15Active TerminationsEE290C Lecture 3 16AC vs. DC Termination• With diff. can terminate to complement• High Z Æ lower power• See more shortly• TX sets common-mode• Can be inconvenient • May need wide CM range• AC-coupled + AC-term• Places some requirements on data thoughRACRxRxRACVCMVCMRCMRCMEE290C Lecture 3 17TX Design: Series vs. Parallel TerminationEE290C Lecture 3 18Alphabet Soup• LVDS, CML• GTL, GTL+, RSL, …• VM, CM• HCM, LCM• All same basic principles• Look at two representative circuits to understand some of the more fundamental tradeoffsEE290C Lecture 3 19CML TX + RX TermIo = - 21mAZo = 50ΩZo = 50ΩRxTxDouble-terminated50Ω50ΩVDDVDDon-chipEE290C Lecture 3 20Side Note: Pre-DriverEE290C Lecture 3 21CML Power ConsumptionEE290C Lecture 3 22Differential VM TX + RX• Main motivation: can reduce power for same swing/supplyEE290C Lecture 3 23Simplified Model And PowerEE290C Lecture 3 24Bad News: Extra Complexity• Driver impedance (termination) now set totally by devices• Some sort of impedance control is critical• “High-swing” driver:EE290C Lecture 3 25Low-Swing VM Driver• Old standards often required large swings (>1V diff. p2p)• More modern designs use much lower swings (~200-400mV diff. p2p) to save power• Low-swing VM driver:EE290C Lecture 3 26Impedance ControlEE290C Lecture 3 27Another ApproachEE290C Lecture 3 28Serialization: Input vs. Output• On-chip clocks often slower than off-chip data-rates• Need to take a set of parallel on-chip data and serialize it• Can serialize either at input of TX or at final outputEE290C Lecture 3 29Serialization: Input vs. Output• Input ser. requires on-chip circuitry to run at full line rate• May lead to high power consumption• In older technologies (0.35um) was hard to support high-freq. clocks• Output ser. noved burdenat pad• At the time was highest BW• Limit in both designs: edge rate• Either for the clock or for the data outout_bRTERMRTERMx 8d0d0ck3D0 D1 D2data(ck0)clock(ck3)EE290C Lecture 3 30Basic TX Final Notes• Usually need many peripheral controls• Zo, edge-rate, etc.• Keep tuning out of the high-speed signal path• P(High-speed, low res. + low-speed, high-res.) << P(high-speed, high-res.)EE290C Lecture 3 31Basic TX Final Notes• Lots of research focused on reduced signaling power • I.e., power spent by actual final driver• Watch out for “overhead” (pre-drivers)• Especially with emerging low-swing designs, overhead can actually dominate• Psig(400mV diff. p2p):• Pdigital(100 min. sized inverters @ 10GHz):• More on this later EE290C Lecture 3 32Basic RX• Simplest: RX is just a comparator @ fbit• (Clocking later)• Key things to watch out for:• High sensitivity (low noise, low offset/hysteresis)• Common-mode input range• Supply/common-mode rejection• Max. clock rate• Power consumptionEE290C Lecture 3 33Typical DesignEE290C Lecture 3 34StrongArm ReviewEE290C Lecture 3 35Higher