1EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical InterfacesLecture 23Case StudiesDisk Drive Read/Write ChannelsBorivoje NikolićApril 13, 2004.2AnnouncementsHomework #3 (the last one!) posted, due in 10 daysFeedback on project, e-mailed to you today23OutlineWrap up EthernetDisk-drive signal processing32‘Marvel of Technology’333Disk Drives1956 IBM engineers in San Jose introduced the first computer disk storage systemThe 305 RAMAC (Random Access Method of Accounting and Control) could store five million characters (five megabytes) of data on 50 disks, each 24 inches in diameter.34Today’s DisksHitachi (IBM) Travelstar 70 Gb/in2Experimental densities: 100+Gb/in2; every square inch of disk space could hold 12 GB -- nearly as much data as a three 5.25-inch diameter DVD-ROMs. (4.7 GB per surface) or 20 CD-ROMs (each 650 MB). Desktop drives 300 GBNotebook drives 80 GBMicrodrive (1-inch) > 4 GB.435Trends in Magnetic Disk DrivesExponential growth in capacity is due to:reduction of head flying heightreduction of the gap size in the headreduction of the media thicknessadvanced signal processing methodsadvanced digitalintegrated circuitsAreal density of datain disk drives:101001000100001000001985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005YearAreal Density [Mb/in2]Super Paramagnetic Limit30Gb/in2 Demo3 Gb/in2 Demo1 Gb/in2 Demo60% CGR30% CGR36IBM’s Areal Densitieshttp://www.storage.ibm.com/technolo/grochows/grocho01.htm537Areal Density Trends0.010.11101001000100001000001960 1965 1970 1975 1980 1985 1990 1995 2000 2005MR Head/ PRMLTechnologies30% CGR60% CGRAreal Density (Mbits/sq. in.)TimeH.ThaparGMR Head38Datarate Trends in Disk DrivesSource: ISSCC + vendors’ web sites101001000100001990 1992 1994 1996 1998 2000 2002YearData Rate [Mb/s]Data rate increase throughtechnology scaling Data rate trendsin read channels639Flight HeightRotation speeds: 4500 – 15000 rpm40Price Trends741Magnetic Recording FundamentalsMagnetic Disk Track RecordingMagnetization LevelsDetected signal in the Head42Magnetic Recording FundamentalsReducedAmplitudePeakShiftIsolatedPulsesSuperposedPulsesIncreased recording density results in:• reduced peak amplitude•peak shift843Lorentzian Pulse-2 -1.5 -1 -0.5 0 0.5 1 1.5 200.10.20.30.40.50.60.70.80.91Normalized Time t/PW50Amplitude of Step ResponsePW50250211)(+=PWttsLorentzian:44Bandlimited ChannelsSpectral control(ISI control)SNR limitationTowards ShannoncapacityEqualization- Partial responseChannel coding- Trellis/Parity codingCombined coding andEqualization- Iterative codingGoing to 1Tb/in2density will lower the SNR by another 6dB945Signal EqualizationLorenzian PulseEqualization (1−D)(1+D)n1.00.5PW50PR4EPR4 E2PR4(1-D)(1+D)(1-D)(1+D)2(1-D)(1+D)311213()250211+=PWttlUser density = PW50/T460 5 10 15 20 25 30 35 40 45 50-1-0.8-0.6-0.4-0.200.20.40.60.81TimeAmplitudeRecording Channel Input/Output PW50/T = 1.40 5 10 15 20 25 30 35 40 45 50-1-0.8-0.6-0.4-0.200.20.40.60.81Tim eAmplitudeRecording Channel Input/Output PW50/T = 3.0Signal ResponseSimulated readback signalUser density = 1.4 User density = 3.01047Amplitude Spectra0.000.200.400.600.801.001.201.400.000.040.080.120.160.200.240.280.320.360.400.440.48Normalized FrequencyA m plitu depw50/T=1.0pw50/T=1.4pw50/T=1.8pw50/T=2.2pw50/T=2.6pw50/T=3.048Equalization Targets0.000.200.400.600.801.001.201.401.601.802.000.00 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 0.44 0.48FrequencyMagnitudePR4(n=1)E2PR4(n=3)EPR4(n=2)1149Read Channel Building Blocks50Eye DiagramsPR4EPR41251Maximum Likelihood Detection52The Viterbi DetectorEqualization Response Memory StatesPR4 1−D224 (2)EPR4 (1−D)(1+D)238E2PR4 (1−D)(1+D)3416Alternative is to use DFE;not used in practice because of error propagation1353Error DistancesChannel input error sequence:)()(ˆ)( DxDxDex−=Channel output error sequence:)()(ˆ)( DyDyDey−=Squared Euclidean error distance:() ()()222)( DhDeDeEdxy==54Error Probability Probability of misdetection of sequence Skby Sk’ is a function of error distance, dKPerformance of the PRML system is determined by the minimum distance error eventsσ≈2minmindQKPdeQ () - Error functionError event distancespectrum1455Signal Processing TrendsPEAK DETECTMFM(2,7)(1,7)PRMLEPRMLPARITY CODINGd=0 ord=1DensityTimeANALOG DIGITALE PRML, GEnPRMLnTURBO CODINGd=0H. Thapar56Current Implementation ApproachesFunction Approach System Architecture EPR, E2PR, or generalized E2PR with16/17 or 8/9 codesEqualization Digital FIR, analog FIR, orcontinuous-time filterADC Flash, typically 6 bitsDetection Full Viterbi detector or Viterbidetector with post-processorGain control First-order loop with digital or analogintegrationTiming Recovery Second-order PLL using synchronousor interpolated timing1557Parity-Coded Channel…P(D)+ViterbiDetectorDelayErrorCorrelateCheckParityMaximumCorrectErrorDetect ErrorDetermine Likely Error LocationData-rknkxk58Architecture #1READSIGNALVGAVITERBIDETECTTIMINGCONTROLGAINCONTROLDETECTEDDATALow passfilterFIREq.Key Features: • All analogSSI, ’90-’971659Architecture #2READSIGNALVGAVITERBIDETECTTIMINGCONTROLGAINCONTROLADCDETECTEDDATALow passfilterFIREq.Key Features: • Analog FIR equalizer• 40-levels in ADCLucent60Architecture #3Key Features: • Digital FIR equalizer• Full 6-bit ADCREADSIGNALVGAVITERBIDETECTTIMINGCONTROLGAINCONTROLADCDETECTEDDATALow passfilterFIREq.Dominant:TI (SSI), Marvell, Datapath, IBM1761Architecture #4Key Features: • Digital FIR equalizer• Interpolated timing recovery• Full 6-bit ADC with >(1/T) samples/sec.READSIGNALVGAVITERBIDETECTTIMINGCONTROLGAINCONTROLADCDETECTEDDATALow passfilterFIREq.InterpolationfilterCirrus Logic62Design Examples1st generation chip170 Mb/s, 1.3W, 5V, 27.5mm2, 0.56mmPublished in 1997 ISSCC Paper 19.72nd generation chip240 Mb/s, 1.4W, 5V, 18.5mm2, 0.54mmUnpublished3rd generation chip400 Mb/s, 1.1W, 3.3V, 13.5mm2, 0.29mmPublished in 1999 ISSCC Paper 2.2H. Thapar, et al, CICC’981863Analog Front-EndPre-equalization in analog domain64Design ChallengesOne of the first Systems-on-a-Chip (SoC)> 2Gb/s ratePower limited (<2W, preferably 1W), inexpensive (<$2.5)Single step vs. lookahead/parallelReduced SNR, complex detectionIntegration with controller gives opportunities for more powerful coding and processingIterative decoders (Turbo, LDPC)1965Architectural ChoicesEqualizer6-10 taps, >1Gb/sChoices of interleaving, pipelining, recoding, carry-save“Infinite”