EM84502PS/2 MOUSE CONTROLLER1* This specification are subject to be changed without notice.6.18.1998EM84502PS/2 MOUSE CONTROLLERGENERAL DESCRIPTIONThe EM84502 Mouse Controller is specially designed to control PS/2 mouse device.This single chip caninterface three key-switches and four photo-couples direct to 8042. EM84502 can receive command and echostatus or data format which are compatible with IBM PS/2 mode mouse. Key debouncing circuit is providedto prevent false entry and improve the accuracy.In the conventional mouse, a great number of noises are generated when the grid is partially closed or opened.These noise are usually mistaken for movement signals by conventional mouse controller and the cursor of thedispaly screen is thus moved frequently up and down or back and forth. This will consumes a great amount ofenergy.The EM84502 PS/2 mouse controller provides noise immunity circuits to eliminate these noisein order to reduce energy consumption.FEATURES• Being compatiable with PS/2 mouse mode.• Built-in noise immunity circuit.• Low power dissipation.• RC oscillation.• Three key-switches and four photo-couples inputs.• Both key-press and key-release debounce interval 12 ms.• Through three key-switches input, EM84502 can exert seven different output.• The motion detector of the EM84502 could sense 8 m/sec maximun with 200 DPI wheels.APPLICATIONS• Optical mouse or pen-mouse.• Mechanical mouse or pen-mouse.• Optomechanical mouse or pen-mouse.• Mechanical track ball.• Optomechanical track ball.PIN ASSIGNMENT* (Under developed)VDDOPNCNCOSC.OUTCLKDATAVSS12345678161514131211109OSCRY2Y1X2X1LMREM84502BPVDDOPNCNCOSC.OUTCLKDATAVSS12345678161514131211109OSCRY2Y1X2X1LMREM84502BM*VDDOPOSC.OUTCLKDATAVSSR1234567141312111098OSCRY2Y1X2X1LMEM84502APVDDOPOSC.OUTCLKDATAVSSR1234567141312111098OSCRY2Y1X2X1LMEM84502AMEM84502PS/2 MOUSE CONTROLLER2* This specification are subject to be changed without notice.6.18.1998VDDPowerOP I X, Y inputs.Floating : Comparator input.GND : Schmitt trigger input.Short to OSC OUT : Testing Mode.OSCOUT O Clock output.CLK I/O 8042 auxiliary port CLK line.DATA I/O 8042 auxiliary port DATA line.VSSGroundR I Three key-switches exert seven different combinations totally. Both key-pressedM and key-released signals will be sent accomplanied with horizontal and verticalL state. The status of the key-switches will be preserved, whenever the value ofhorizontal or vertical counters will present at DATA. And the debounce intervalfor both key-press and key-release is 12 ms.X1 I Four photo-couple signals denote UP, DOWN, LEFT, and RIGHT state.X2 During the scaning period, as long as the photo-couples change their states, theY1 value of vertical or horizontal counter will increase or decrease accordingly.Y2OSCR I 30 Kohm ±5% pull low for 35 KHz oscillation.FUNCTION DESCRIPTIONSA) Operating modeThere are four operating modes in PS/2 mouse:i). Reset Mode:In this mode a self-test is initiated during power-on or by a Reset command. After reset signal, PS/2mouse will send:1). Completion code AA & ID code 00.FUNCTIONAL BLOCK DIAGRAMDETECTORMOTIONIMMUNITYNOISEDEBOUNCECONVERTERDATADECODERCOMMANDCOUNTERTIMINGCONTROLLERDATAI/OSYSTEMCLOCKGENERATOROPX1X2Y1Y2LMROSCROSC OUTDATACLKSymbol I/O FunctionPIN DESCRIPTIONSEM84502PS/2 MOUSE CONTROLLER3* This specification are subject to be changed without notice.6.18.19982). Set default:sampling rate: 100 reports/snon-autospeedstream mode2 dot/countdisableii). Stream Mode:The maximum rate of transfer is the programmed sample rate.Data report is transmitted if1). switch is pressed2). movement has been detectiii). Remote Mode:Data is transmitted only in response to a Read Data command.iv). Wrap Mode:Any byte of data sent by the system, except hex EC ( Reset wrap mode ) or hex FF ( Reset ), is returnedby EM84502.B). PS/2 Mouse Data Report:i). In stream mode: A data report is sent at the end of a sample interval.ii). In remote mode: A data report is sent in response to Read Data command.iii). Data report format:Byte Bit Description1 0 Left button status; 1 = pressed1 Right button status; 1 = pressed2 Middle button status; 1 = pressed3 Reserve4 X data sign; 1 = negative5 Y data sign; 1 = negative6 X data overflow; 1 = overflow7 Y data overflow; 1 = overflow2 0-7 X data ( D0 - D7 )3 0-7 Y data ( D0 - D7 )C) PS/2 mouse Data Transmission:i). EM84502 generates the clocking signal when sending data to and receiving data from the system.ii). The system requests EM84502 receive system data output by forcing the DATA line to an inactive level and allowing CLK line to go to an active level.iii). Data transmission frame:EM84502PS/2 MOUSE CONTROLLER4* This specification are subject to be changed without notice.6.18.1998Bit Function1 Start bit ( always 0 )2-9 Data bits ( D0 - D7 )10 Parity bit ( odd parity )11 Stop bit ( always 1 )iv). Data Output ( data from EM84502 to system ):If CLK is low ( inhibit status ) , data is no transmission.If CLK is high and DATA is low ( request-to-send ), data is updated. Data is received from the systemand no transmission are started by EM84502 until CLK and DATA both high. If CLK and DATA are bothhigh, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edgeof CLK. During transmission, EM84502 check for line contention by checking for an inactive level on CLKat intervals not to exceed 100u sec. Contention occurs when the system lowers CLK to inhibit EM84502output after EM84502 has started a transmission. If this occurs before the rising edge of the tenth clock,EM84502 internal store its data in its buffer and returns DATA and CLK to an active level. If the contentiondoes not occur by the tenth clock, the transmission is complete.Following a transmission, the system inhibits EM84502 by holding CLK low until it can service the inputor until the system receives a request to send a response from EM84502.v). Data Input ( from system to EM84502 ):System first check if EM84502 is transmitting data. If EM84502 is transmitting, the system can overridethe output forcing CLK to an inactive level prior to the tenth clock. If EM84502 transmission is beyondthe tenth clock, the system receives the data. If EM84502 is not transmitting or if the system choose tooverride the output, the system force CLK to an inactive level for a period of not less than 100µ sec whilepreparing for output.