Prelude to MultiprocessingCPUIDPentium EFLAGS registerBut what if there’s no EFLAGS?Detecting 32-bit processorsDetecting EFLAGSTesting for ID-bit ‘toggle’How does CPUID work?Version and FeaturesSome Feature Flags in EDXMultiprocessor SpecificationMP Floating Pointer StructureThe processor’s Local-APICEach CPU has its own timer!Timer’s Local Vector TableIn-class exerciseIn-class exercise #2Prelude to MultiprocessingDetecting cpu and system-board capabilities with CPUID and the MP Configuration TableCPUID•Recent Intel processors provide a ‘cpuid’ instruction (opcode 0x0F, 0xA2) to assist software in detecting a CPU’s capabilities•If it’s implemented, this instruction can be executed in any of the processor modes, and at any privilege level•But it may not be implemented (e.g., 8086, 80286, 80386)Pentium EFLAGS register0 0 0 0 0 0 0 0 0 0IDVIPVIFACVMRF0NTIOPLOFDFIFTFSFZF0AF0PF1CF31 1615 021Software can ‘toggle’ the ID-bit (bit #21) in the 32-bit EFLAGS register if the processor is capable of executing the ‘cpuid’ instructionBut what if there’s no EFLAGS?•The early Intel processors (8086, 80286) did not implement 32-bit registers •The FLAGS register was only 16-bits wide•So there was no ID-bit that software could try to ‘toggle’•How can software be sure that the 32-bit EFLAGS register exists within the CPU?Detecting 32-bit processors•There’s a subtle difference in the way the logical shift/rotate instructions work when register CL contains the shift-factor•On the 32-bit processors (e.g., 80386+) the value in CL is truncated to 5-bits, but not so on the 16-bit CPUs (8086, 80286)•Software can exploit this distinction, in order to tell if EFLAGS is implementedDetecting EFLAGS; Here’s a test for the presence of EFLAGSmov ax, #0xFFFF; a nonzero value mov cl, #32 ; shift-factor of 32shl ax, cl ; do logical shiftor ax, ax ; test result in AXjnz is32bit ; EFLAGS presentjmp is16bit ; EFLAGS absentTesting for ID-bit ‘toggle’; Here’s a test for the presence of the CPUID instructionpushfd ; copy EFLAGS contentspop eax ; to accumulator registermov edx, eax ; save a duplicate imagexor eax, 0x00200000 ; toggle the ID-bit (bit 21)push eax ; copy revised contentspopfd ; back into EFLAGSpushfd ; copy EFLAGS contentspop eax ; back into accumulatorxor eax, edx ; do XOR with prior valuetest eax, 0x00200000 ; did ID-bit get toggled?jnz y_cpuid ; yes, can execute ‘cpuid’jmp n_cpuid ; else ‘cpuid’ unimplementedHow does CPUID work?•Step 1: load value 0 into register EAX•Step 2: execute ‘cpuid’ instruction•Step 3: Verify ‘GenuineIntel’ character-string in registers (EBX,EDX,ECX)•Step 4: Find maximum CPUID input-value in the EAX registerVersion and Features• load 1 into EAX and execute CPUID•Processor model and stepping information is returned in register EAXExtendedFamily IDExtendedModel IDTypeFamilyIDModelSteppingID3 07 411 813 1219 1627 20Some Feature Flags in EDXHTTAPICPSEVME9328HTT = HyperThreading Technology (1 = yes, 0 = no)APIC = Advanced Programmable Interrupt Controller on-chip (1 = yes,0 = no)PSE = Page-Size Extensions (1 = yes, 0 = no)Virtual-8086 Mode Enhancements (1 = yes, 0 = no)1Multiprocessor Specification•Industry standard allowing OS software to use multiple processors in a uniform way•Software searches in three regions of the physical address-space below 1-megabyte for a “paragraph-aligned” data-structure of length 16-bytes called the MP Floating Pointer Structure: –Search in lowest KB of Extended Bios Data Area–Search in topmost KB of conventional 640K RAM–Search in the 64KB ROM-BIOS (0xF0000-0xFFFFF)MP Floating Pointer Structure•This structure may contain an ID-number for one a small number of standard SMP system architectures, or may contain the memory address for a more extensive MP Configuration Table whose entries specify a “more customized” system architecture •Our classroom machines employ the latter of these two optionsThe processor’s Local-APIC•The purpose of each processor’s APIC is to allow CPUs in a multiprocessor system to transmit messages among one another and to manage the delivery of interrupts from the various peripheral devices to one or more CPUs in a carefully controlled way•The Local-APIC has a variety of registers which are ‘memory mapped’ to paragraph-aligned addresses in the 4KB page at 0xFEE00000Each CPU has its own timer!•Four of the Local-APIC registers are used to implement a programmable timer •It can privately deliver a periodic interrupt just to its own CPU–0xFEE00320: Timer Vector register–0xFEE00380: Initial Count register–0xFEE00390: Current Count register–0xFEE003E0: Divider Configuration registerTimer’s Local Vector TableInterruptID-numberMODEMASKBUSY7 01216170xFEE00320In-class exercise•Run the ‘cpuid.cpp’ Linux application (on our course website) to see if the CPUs in our classroom implement HyperThreading (i.e., multiple processors within one CPU)•Then run the ‘smpinfo.cpp’ application, to see if the MP Base Configuration Table has entries for more than one processor•If both results hold true, then we can write our own multiprocessing software in here!In-class exercise #2•Run the ‘apictick.s’ demo (on our website) to observe the APIC’s periodic interrupt drawing bytes onto the screen•It executes for ten-milliseconds (the 8042 is used to create this timed delay)•Try reprogramming the APIC’s Divider Configuration register, to cut the interrupt frequency in half (or to double
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